Atmel AT90S8515-8PI - Page 60

AT90S4414/8515
60
Figure 48. Port B Schematic Diagram (Pin PB4)
Figure 49. Port B Schematic Diagram (Pin PB5)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB4
SPI SS
MSTR
SPE
WP:
WD:
RL:
RP:
RD:
MSTR:
SPE:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI MASTER ENABLE
SPI ENABLE
DDB4
PORTB4
RL
RP
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PB5
R
R
WP:
WD:
RL:
RP:
RD:
SPE:
MSTR
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
SPI ENABLE
MASTER SELECT
DDB5
PORTB5
SPE
MSTR
SPI MASTER
OUT
SPI SLAVE
IN
RL
RP