Atmel AT90S8515-8PI - Page 59

AT90S4414/8515
59
Port B Schematics
Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.
Figure 46. Port B Schematic Diagram (Pins PB0 and PB1)
Figure 47. Port B Schematic Diagram (Pins PB2 and PB3)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PBn
R
R
WP:
WD:
RL:
RP:
RD:
WRITE PORTB
WRITE DDRB
READ PORTB LATCH
READ PORTB PIN
READ DDRB
DDBn
PORTBn
SENSE CONTROL
TIMERn CLOCK
SOURCE MUX
CSn2
CSn0
RL
RP
CSn1
n: 0,1