137
7679H–CAN–08/08
AT90CAN32/64/128
Table 13-3 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Note: 1. A special case occurs when OCnA/OCnB/OCnC equals TOP and
COMnA1/COMnB1/COMnC1 is set. See “Phase Correct PWM Mode” on page 130. for more
details.
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see Table 13-4. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types
of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page 126.).
Table 13-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
(1)
COMnA1/COMnB1/
COMnC1
COMnA0/COMnB0/
COMnC0
Description
00
Normal port operation, OCnA/OCnB/OCnC
disconnected.
01
WGMn3=0: Normal port operation,
OCnA/OCnB/OCnC disconnected.
WGMn3=1: Toggle OCnA on Compare Match,
OCnB/OCnC reserved.
10
Clear OCnA/OCnB/OCnC on Compare Match when
up-counting.
Set OCnA/OCnB/OCnC on Compare Match when
downcounting.
11
Set OCnA/OCnB/OCnC on Compare Match when up-
counting.
Clear OCnA/OCnB/OCnC on Compare Match when
downcounting.
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