ATtiny15L
36
The Analog Comparator Control And Status Register – ACSR
•
Bit 7 - ACD: Analog Comparator Disable
When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn-off the
analog comparator. This will reduce power consumption in active and idle mode. When changing the ACD-bit, the Analog
Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
•
Bit 6 - ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap voltage of 1.22 ± 0.05V replaces the normal input to the positive pin (AIN0) of the com-
parator. When this bit is cleared, the normal input pin PB0 is applied to the positive pin of the comparator.
•
Bit 5 - ACO: Analog Comparator Output
ACO is directly connected to the comparator output.
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Bit 4 - ACI: Analog Comparator Interrupt Flag
This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACI1 and ACI0. The Analog
Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to
the flag.
•
Bit 3 - ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated.
When cleared (zero), the interrupt is disabled.
•
Bit 2 - Res: Reserved bit
This bit is a reserved bit in the ATtiny15L and will always read as zero.
•
Bits 1,0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are
shown in Table 16.
Note: When changing the ACIS1/ACIS0 bits, The Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in
the ACSR register. Otherwise an interrupt can occur when the bits are changed.
Bit 76543210
$08 ACD ACBG ACO ACI ACIE - ACIS1 ACIS0 ACSR
Read/Write R/W R/W R R/W R/W R R/W R/W
Initial value 0 0 X 0 0 0 0 0
Table 16. ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode
0 0 Comparator Interrupt on Output Toggle
01Reserved
1 0 Comparator Interrupt on Falling Output Edge
1 1 Comparator Interrupt on Rising Output Edge
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