ATtiny15L
54
Low-voltage Serial Programming Algorithm
When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK. When reading data from the
ATtiny15L, data is clocked on the falling edge of SCK. See Figure 34, Figure 35 and Table 27 for timing details. To program
and verify the ATtiny15L in the serial programming mode, the following sequence is recommended (See four byte instruc-
tion formats in Table 26
):
1. Power-up sequence:
Apply power between V
CC
and GND while RESET and SCK are set to “0”. If the programmer can not guarantee that
SCK is held low during power-up, RESET
must be given a positive pulse of at least two MCU cycles duration after SCK
has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the
MOSI (PB0) pin. Refer to the above section for minimum low and high periods for the serial clock input SCK.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the
second byte ($53) will echo back when issuing the third byte of the Programming Enable instruction. Whether the
echo is correct or not, all 4 bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a
positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is
no functional device connected.
4. If a Chip Erase is performed (must be done to erase the Flash), wait t
WD_ERASE
after the instruction, give RESET a
positive pulse, and start over from Step 2. See Table 28 on page 56 for t
WD_ERASE
value.
5. The Flash or EEPROM array is programmed one-byte at a time by supplying the address and data together with the
appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written.
Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait
t
WD_PROG_FL
or t
WD_PROG_EE
, respectively, before transmitting the next instruction. See Table 29 on page 56 for the
t
WD_PROG_FL
and t
WD_PROG_EE
values. In an erased device, no $FFs in the data file(s) needs to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the content at the selected
address at the serial output MISO (PB1) pin.
7. At the end of the programming session, RESET
can be set high to commence normal operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn V
CC
power-off
Data Polling
When a byte is being programmed into the Flash or EEPROM, reading the address location being programmed will give
the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to
determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the
user will have to wait for at least t
WD_PROG_FL
before programming the next Flash byte, or t
WD_PROG_EE
before the next
EEPROM byte. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain
$FF, can be skipped. This does not apply if the EEPROM is reprogrammed without chip-erasing the device. In that case,
data polling cannot be used for the value $FF, and the user will have to wait at least t
WD_PROG_EE
before programming the
next byte. See Table 29 for t
WD_PROG_FL
and t
WD_PROG_EE
values.
Figure 34. Low-voltage Serial Programming Waveforms
MSB
MSB
LSB
LSB
SERIAL CLOCK INPUT
PB2(SCK)
SERIAL DATA INPUT
PB0(MOSI)
SERIAL DATA OUTPUT
PB1(MISO)
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