BASF 6106 - Page 33

ERASENA/
is
switched
always a
certain
delay
tiae
after
WRITE
GATE/.
The
value
of
the erase
current
is
determined
by
the
value of
the re-
sistor R67.
The
delay of
the
erase
current
is
necessary,
because
the
tunnel
erase
gaps are
physicaly
located
behind
the
read/write
gap.
This
causes
the
erase
gap
to
reach
the
sane
place
on
the
track
always
later
than
than the
read/write
gap.
Fig. 2
-
32
shows
the
logic of
the
the
erase
delay
logic.
Fig.
2
-
33
is
a
timing
diagram
for
the
erase delay
logic.
ERASE
OFF
DELAY
GCU
FROM
IK>
CONTROL
PWRONRESET/
WRTENA
ERASE
OK
DELAY
Q-
^FSfCh
WRTENA
ERASE/-
FF
i)
Q
T
i>
ERASESA /
FIGURE 2
-
32
,
ERASE
DELAY LOGIC
WRITE
ENABLE
ERASE ON DLY
ERASE
ENABLE
ERASE OFF
DLY
(320-400) /usee
r*
(900-1050)
yu.ee
FIGURE 2
-
33 . ERASE
DELAY TIMING
2-23