BASF 6106 - Page 38

2.2.9
.
DC-
CONTROL
AND
POWER
ON
RESET
LOGIC
2.
2.
9.
2.
POWER
ON
RESET
LOGIC
2.2.9.
J.
DC-
CONTROL
The
DC-
control
logic
is
shown
on
Fig.
2-4
1
This
logic
monitors
the
DC-
voltages
5 V
and
12V
and
disables
the
write
and
erase
current
source,
if
one
of
these
voltages
is
missing
or
out
of
the
following
limits:
If
5
V
falls
below
4,7
V
,
DC
-
CONTROL
goes
high
and
disables
T3.
If
*-12
V
falls
below
9 V
,T3
is
also
blocked
and
the
write
and
erase
current
inhibited.
The
power
on
reset
logic
is
shown
on
Fig.
2-4
2
.
As
the
-SV
energizes
the
capaci
tor
begins
to
charge
towards
3
V.
As
long
as
the
capacitor
voltage
is
lower
than
the
threshold
voltage
V
t
h
of
the
driver
gate
the
PWRONRESET /-
sig-
nal
is
held
low,
thus
a
40
msec
logic
initi-
alization
pulsCis
developed
(see
Fig.
2-43
).
The
PWRONRESET/-
puis*
provides
the
following:
'
•
Resets
the
ERASE
OFF
Delay
One
Shot.
•
Resets
the
Ready
Detector
Logic.
•
Resets
the
IN
USE-
FF.
WR
I
TE
AND
ERASE
TO
XL
:
RFEM,»
WRITE
LOGIC
R30
5V
R5
CI
33/u
5V
Rb
I
n
tj2
~
2
Y V
l
u
PWRONRESET/
TO
ITE
LOCK
TO
-P
REAIVi
DETECTOR
FIGURE
2-41
.DC-
CONTROL
LOGIC
FIGURE
2
-
42
.
POWER
ON
RESET
LOGIC
5V
POWER
ON
RESET/.
FIGURE
2 - 43
.
TIMING
DIAGRAM
POWER
ON
RESET
28