Bionet BM3 - Page 48

BM3 www.BIO2NET.com
Revision A
- 48 -
Dgital b/d, CPU part
DGND
PORT5
nWBE[0..3]
SPI_TXD
n
X
D
R
E
Q
0
ADDR2
JP1
FH10-50-DR
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
VCC3.3
TDO
E
x
I
N
T
3
nGCS[0..7]
TOUT2
ADDR2
ADDR12
ADDR10
PORT4
BC3
0.1UF/Z
R28
0/J
C12
22PF/J
VCC2.5
XTAL0
nWE
nXDACK0
VDDRTC
DGND
A
D
C
7
nWAIT
TOUT0
ADDR17
ExINT7
nRESET
PORTINCS
R99
4.7K/J
C11
1UF/Z
ADC5
n
G
C
S
2
PORT2
KEY_CS
nGCS0
SPI_TXD
ADC0
ADC5
RTS1
C10
0.1UF/Z 미삽
VCCRTC
VCLK
A
R
E
F
T
ADC6
ADDR20
nGCS4
PORT2
+
C7
10UF/35V
OM1,0=01 : 16bit(nGCS0)
+2.5GND
ADDR[0..22]
TxD0
MCLK
PORTINCS
RxD1
R101
4.7K/J
VSSADC
nWBE1
U1
S3C44B0X01-EDR0
1 2 3 4 5 6 7 8 9 1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
1
0
0
1
0
1
1
0
2
1
0
3
1
0
4
1
0
5
1
0
6
1
0
7
1
0
8
1
0
9
1
1
0
1
1
1
1
1
2
1
1
3
1
1
4
1
1
5
1
1
6
1
1
7
1
1
8
1
1
9
1
2
0
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
A
D
D
R
3
A
D
D
R
2
A
D
D
R
1
A
D
D
R
0
n
C
A
S
0
n
C
A
S
1
n
C
A
S
2
n
C
A
S
3
V
D
D
I
O
V
S
S
I
O
n
W
B
E
0
/
D
Q
M
0
n
W
B
E
1
/
D
Q
M
1
n
W
B
E
2
/
D
Q
M
2
n
W
B
E
3
/
D
Q
M
3
n
O
E
n
W
E
n
G
C
S
0
n
G
C
S
1
n
G
C
S
2
n
G
C
S
3
V
D
D
V
S
S
n
G
C
S
4
n
G
C
S
5
n
G
C
S
6
n
G
C
S
7
S
C
K
E
S
C
L
K
n
W
A
I
T
n
X
D
R
E
Q
0
n
X
D
A
C
K
0
E
x
I
N
T
0
E
x
I
N
T
1
V
D
D
V
S
S
E
x
I
N
T
2
E
x
I
N
T
3
E
x
I
N
T
4
E
x
I
N
T
5
E
x
I
N
T
6
ExINT7
nTRST
TCK
TMS
TDI
TDO
VDDIO
VSSIO
CLKout/GPE0
nRESET
OM0
OM1
OM2
OM3
ENDIAN/CODECLK/GPE8
SIOCLK/nCTS1/IISCLK/GPF8
SIORxD/RxD1/IISDI/GPF7
SIORDY/TxD1/IISDO/GPF6
SIOTxD/nRTS1/IISLRCK/GPF5
IISDA/GPF1
IISCL/GPF0
VDD
VSS
XTAL0
EXTAL0
PLLCAP
EXTCLK
TOUT0/GPE3
TOUT1/TCLK/GPE4
TOUT2/TCLK/GPE5
TOUT3/VD6/GPE6
TOUT4/VD7/GPE7
VSSIO
VSSADC
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
A
I
N
6
A
I
N
7
A
R
E
F
T
A
R
E
F
B
A
V
C
O
M
V
D
D
A
D
C
X
T
A
L
1
E
X
T
A
L
1
V
D
D
R
T
C
V
S
S
I
O
V
F
R
A
M
E
/
G
P
D
7
V
M
/
G
P
D
6
V
L
I
N
E
/
G
P
D
5
V
C
L
K
/
G
P
D
4
V
D
3
/
G
P
D
3
V
D
2
/
G
P
D
2
V
D
1
/
G
P
D
1
V
D
0
/
G
P
D
0
R
x
D
0
/
G
P
E
2
T
x
D
0
/
G
P
E
1
D
A
T
A
3
1
/
n
C
T
S
0
/
G
P
C
1
5
D
A
T
A
3
0
/
n
R
T
S
0
/
G
P
C
1
4
D
A
T
A
2
9
/
R
x
D
1
/
G
P
C
1
3
D
A
T
A
2
8
/
T
x
D
1
/
G
P
C
1
2
D
A
T
A
2
7
/
n
C
T
S
1
/
G
P
C
1
1
D
A
T
A
2
6
/
n
R
T
S
1
/
G
P
C
1
0
D
A
T
A
2
5
/
n
X
D
R
E
Q
1
/
G
P
C
9
D
A
T
A
2
4
/
n
X
D
A
C
K
1
/
G
P
C
8
V
D
D
V
S
S
D
A
T
A
2
3
/
V
D
4
/
G
P
C
7
D
A
T
A
2
2
/
V
D
5
/
G
P
C
6
D
A
T
A
2
1
/
V
D
6
/
G
P
C
5
D
A
T
A
2
0
/
V
D
7
/
G
P
C
4
D
A
T
A
1
9
/
I
I
S
C
L
K
/
G
P
C
3
D
A
T
A
1
8
/
I
I
S
D
I
/
G
P
C
2
D
A
T
A
1
7
/
I
I
S
D
O
/
G
P
C
1
D
A
T
A
1
6
/
I
I
S
L
R
C
K
/
G
P
C
0
D
A
T
A
1
5
D
A
T
A
1
4
DATA13
DATA12
DATA11
DATA10
VDDIO
VSSIO
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR24/GPA9
VDD
VSS
ADDR23/GPA8
ADDR22/GPA7
ADDR21/GPA6
ADDR20/GPA5
ADDR19/GPA4
ADDR18/GPA3
ADDR17/GPA2
ADDR16/GPA1
ADDR15
ADDR14
ADDR13
ADDR12
VSSIO
ADDR11
ADDR10
ADDR9
ADDR8
ADDR7
ADDR6
ADDR5
ADDR4
DGND
A
D
D
R
3
E
x
I
N
T
4
DATA5
R10
4.7K/J
VCC2.5
VCC3.3
ADDR13
nCAS3
CTS1
VCC2.5
ADDR4
MCLK
VLINE
V
D
D
R
T
C
DATA10
DATA8
BC5
0.1UF/Z
ADC0
PORT0
nWBE3
DATA7
OM1
nXDACK1
nGCS4
R30
4.7K/J
R20
10K/J
IIC_SCL
ADC2
n
G
C
S
6
nCAS0
n
C
A
S
0
DATA10
VDDADC
ADDR3
nRESET
DATA11
DATA3
DGND
OM0
DGND
DGND
n
X
D
R
E
Q
1
SPI_CLK
nGCS[0..7]
ADDR5
R12100/J
TxD1
V
D
0
nWBE1
TxD0
ExINT0
ADDR3
nXDREQ1
PORT5
R9
47K/J
R24
4.7K/J
R22
4.7K/J
SPI_CLK
IISCLK
TOUT1
V
D
5
ADDR21
IIC_SDA
VCC3.3
V
D
7
UART_CS1
ADDR8
C13
22PF/J
V
F
R
M
VD6
ExINT4
R107
4.7K/J
R104100/J
J4
5267-4
1
2
3
4
ADDR16
SPI_RXD
DATA7
+2.5GND
n
O
E
R
T
S
1
n
X
D
A
C
K
0
ADDR11
ADDR6
PORT3 R15100/J
DATA[0..15]
A
R
E
F
B
VD[0..7]
IISDO
IISLRCK
nGCS1
TxD1
TOUT4
nWE
PORT1
n
G
C
S
0
ADDR6
PORT1
GND
+2.5GND
UART_CS0
n
X
D
A
C
K
1
ADC4
ADDR6
nXDACK1
D15
WSD425
S1
TCAT SW
R
T
S
0
V
M
SPI_TXD
IIC_SCL
n
W
B
E
0
nWBE3
ADDR0
BC12
0.1UF/Z
VCC7.5
VCC2.5
nCAS[0..3]
DATA9
VCC5.0
ADDR9
DATA[0..15]
ADDR14
Little
IISDO
RTS0
XTAL1
nWBE2
DGND
ADC3
nXDACK1
DATA4
ADDR18
C15
1UF/Z
DGND
ADDR22
R100
4.7K/J
VCC3.3
OM3
TMS
ADDR11
ADDR20
DATA1
nGCS6
EXTCLK
R126
220/J
DGND
DATA1
OM2
ADDR5
R29 10/J
R106 22/J
VCC3.3
VCC3.3
IIC_SDA
ADDR4
I
I
S
D
I
UART_CS1
R18
10K/J
VCC2.5
VCC7.5
VCC3.3
RTS0
nGCS3
ADDR5
PORT4
VCC3.3
DATA2
ADDR4
R23 10/J
DGND
SCKE
UART_CS1
PORT4
nTRST
nXDREQ1
nWBE[0..3]
T
x
D
1
IISDI
DATA6
DATA0
nOE
TOUT4
OM3
OM0
DGND
V
D
2
ADDR19
DATA0
BC6
0.1UF/Z
DGND
ADC1
TOUT3
D
A
T
A
1
4
DATA7
VCC3.3
V_PWR
DATA0
nWAIT
I
I
S
D
O
E
x
I
N
T
2
ENDIAN
RxD0
DATA13
E
X
T
A
L
1
I
I
S
C
L
K
D
A
T
A
1
5
V
C
L
K
OM1
DGND
V
D
3
DATA5
ADC0
BC11
0.1UF/Z
R19
10K/J
ExINT0
IIC_SDA
VD5
V
D
D
A
D
C
UART_CS0
CTS0
VCC3.3
T
x
D
0
ADDR22
R25
4.7K/J
BC1
0.1UF/Z
VCC3.3
DATA8
nWBE2
ExINT1
ExINT5
SPI_CLK
nWBE0
DATA5
U2
74HC138
1
2
3
6
4
5
15
14
13
12
11
10
9
7
A
B
C
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
B1
0/J
DGND
IISLRCK
TOUT1
TOUT2
RxD0
ADC4
nXDREQ1
TCK
EXTAL0
R
x
D
0
n
G
C
S
4
V
L
I
N
E
DGND
POWER_CHK
ADDR19
BC10
0.1UF/Z
U5A
74HC14
1 2
1
4
7
BC4
0.1UF/Z
VLINE
n
W
E
RTS1
R105100/J
TCK
VD1
nWE
BC39
0.1UF/Z 미삽
nTRST
VSSADC
ADDR7
PORT5
OM3,2=00 : XTAL,PLL ON
VCC3.3
nGCS6
n
G
C
S
1
ExINT[0..7]
OM2
VD[0..7]
DATA2
nGCS5
ADDR17
+2.5GND
RxD1
ADDR12
SCLK
nXDACK0
VD[0..7]
RTS1
C
T
S
1
VCLK
V_PWR
TDI
ADDR1POWER_CHK
DATA12
PORT0
VCC2.5
ExINT[0..7]
nGCS0
KEY_CS
DATA7
+
C6
10UF/35V
VCC2.5
E
x
I
N
T
1
EXTAL1
C9
750PF/J
R27
4.7K/J
DGND
nWAITDATA5
ADC3
OM3,2=01 : EXTCLK,PLL ON
DGND
ADC1
A
D
C
6
BC2
0.1UF/Z
nOE
DATA9
RESET
DATA1
VBAT
SCLK
PORT2
ADDR8
wRESET
VCC3.3
S
C
K
E
nOE
ADDR3
CTS1
U9D
74HC14
9 8
1
4
7
R14100/J
V_PWR
n
C
A
S
3
S
C
L
K
VCC3.3
ExINT[0..7]
PORT0
UART_CS0
ExINT6
WDT_RST
DATA3
C
T
S
0
ADDR4
BC7
0.1UF/Z
nCAS[0..3]
TMS
DGND
VCC3.3
GND
ADC6
CTS0
ADC0
SPI_RDY
V
D
1
VD2
TxD0
BT1
BH2-B
nXDACK0
DATA0
CTS0
ADDR16
R31 4.7K/J
E
x
I
N
T
0
DATA11
n
C
A
S
2
ADC2
DATA6
ADDR9
ADDR13
ADDR21
EXTCLK
DATA6
U4
CAT1163J-28
1
2
3
4
8
7
6
5
WDI
RESET
WP
GND
VCC
RESET
SCL
SDA
n
W
A
I
T
R11
4.7K/J
ADC5
VD7
ENDIAN
ExINT2
ADDR15
DATA14
ADDR7
nGCS2
DATA4
DGND
VCC3.3
V
D
6
n
W
B
E
3
ADDR0
nGCS1
SOT23
nGCS[0..7]
RESET
EXTCLK
VD3
U21
18.432MHz
1 4
2 3
NC VCC
GND OUT
R13100/J
VCC3.3
ADDR7
X
T
A
L
1
PLLCAP
ADDR15
C4
10NF/Z
VCC5.0
ADDR[0..22]
ADDR18
ADC1
R97
0/J 미삽
E
x
I
N
T
5
A
V
C
O
M
VFRM
VD0
E
x
I
N
T
6
A
D
D
R
2
ADDR[0..22]
+ C8
10UF/35V
VCC3.3
IIC_SCL
IISCLK
VCC2.5
n
G
C
S
5
ADDR14
A
D
D
R
1
PORT3
IIC_SDA
ExINT3
ADDR10
BC9
0.1UF/Z
U3
74HC245MTC20
2
3
4
5
6
7
8
9
19
1
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
G
DIR
B1
B2
B3
B4
B5
B6
B7
B8
VCC3.3
VCC3.3
nRESET
PORT3
V
D
4
ADDR1
RTS0
VCC3.3
VCC3.3
KEY_CS
nRESET
DATA6
nGCS7
PORT1
BC8
0.1UF/Z
C3
10NF/Z
C5
10NF/Z
VCC3.3
VCC3.3
SCKE
ADC3
MCLK
DATA2
VCC3.3
nXDREQ0
DGND
nRESET
nWBE0
VD4
TM
ADDR5
TOUT1
DGND
nCAS[0..3]
n
W
B
E
2
nCAS1
DATA3
R16
4.7K/J
X1
32.768kHz
3 4
IISDI
CTS1
TDI
nWBE[0..3]
nXDREQ0
R26 4.7K/J
+2.5GND
ADC2
nXDREQ0
ExINT7
ADC4
R96
30K/J 미삽
n
G
C
S
7
n
C
A
S
1
nCAS2
DATA1
DATA2
C45
0.1UF/Z
VFRM
n
G
C
S
3
EXTCLK
TOUT4
DATA4
DGND
RxD0
DATA15
DATA4
I
I
S
L
R
C
K
wRESET
XTAL0
DATA12
R
x
D
1
DATA[0..15]
A
D
D
R
0
IIC_SCL
RESET
DATA13
R21
4.7K/J
C14
1UF/Z
VCC3.3
DGND
n
W
B
E
1
TM
DATA3