Figure 34. 32-Bit PCI Connector
Table 12. 32-Bit PCI Connector Pin Assignments
Pin Name Description Pin Name Description
B1 –12V –12 VDC A1 TRST_L Test Logic Reset
B2 TCK Test Clock A2 +12V +12 VDC
B3 GND Ground A3 TMS Test Mode Select
B4 TDO Test Data Output A4 TDI Test Data Input
B5 +5V +5 VDC A5 +5V +5 VDC
B6 +5V +5 VDC A6 INTA_L Interrupt A
B7 INTB_L Interrupt B A7 INTC_L Interrupt C
B8 INTD_L Interrupt D A8 +5V +5 VDC
B9 PRSNT1_L Reserved A9 RESV Reserved VDC
B10 RESV Reserved VDC A10 +5V +V I/O (+5 V)
B11 PRSNT2_L Reserved A11 RESV Reserved VDC
B12 GND Ground A12 GND Ground
B13 GND Ground A13 GND Ground
B14 RESV Reserved VDC A14 RESV Reserved VDC
B15 GND Ground A15 RESET_L Reset
B16 CLK Clock A16 +5V +V I/O (+5 V)
B17 GND Ground A17 GNT_L Grant PCI use
B18 REQ_L Request A18 GND Ground
B19 +5V +V I/O (+5 V) A19 PME_L Power Management Event
B20 AD31 Address/Data 31 A20 AD30 Address/Data 30
B21 AD29 Address/Data 29 A21 +3.3V +3.3 VDC
B22 GND Ground A22 AD28 Address/Data 28
B23 AD27 Address/Data 27 A23 AD26 Address/Data 26
B24 AD25 Address/Data 25 A24 GND Ground
B25 +3.3V +3.3VDC A25 AD24 Address/Data 24
B26 C/BE3_L Command, Byte Enable 3 A26 IDSEL Initialization Device Select
B27 AD23 Address/Data 23 A27 +3.3V +3.3 VDC
Appendix - 16
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