1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
A A
B B
C C
D D
Cold boot/Optimus: 1V8_AONĺ1V8_RUNĺNVVDDĺNVVDDS ĺPEX_VDDĺFBVDDQ
GC6 2.1 Exit: 1V8_RUNĺNVVDD_LĺNVVDD_SĺPEX_VDD or 1V8_RUNĺNVVDD_LĺNVVDD_S & PEX_VDD
POWER RAIL State in GC6
1V8_AON
1V8_MAIN
PEX&1.05V
NVVDD
ON
OFF
OFF
OFF
close to ICP lace resistors
GC6 2.1 Control Signals
1.1V8_MAIN_EN
2.GC6_FB_EN
3.GPU_EVENT#
4.GPU_PEX_RST_HOLD#
5.SYS_PEX_RST_MON#
GPU
1V8_MAIN_EN
GC6_FB_EN
VR Complex
1V8_AON
1V8_MAIN
NVVDD
PEX&1.05V
NVVDDS
EC/PCH
GPU_PWR_EN
GPU_EVENT#
GPU_RST#
PLATFORM_RST#
SYS_PEX_RST_MON#
GPU_PEX_RST_HOLD#
GPU_PEX_RST#
FBVDD/Q
NVVDDS
NVVDD
GC6 2.1 - VR Complex
1. GPU_PWR_EN
2. 1V8_MAIN_EN
3. GC6_FB_EN
GPU
GPU_PWR_EN
(SYSTEM)
1V8_AON
1V8_AON
1V8_MAIN_EN 1V8_MAIN
PEX&1.05V
NVVDD
FBVDD/Q
EN
EN
EN
EN
EN
PGOOD
PGOOD PGOOD
PGOOD
GC6_FB_EN
PGOOD
DG P.93 note: t1(from 1V8_RUN_EN to PEX_VDD/NVVDD_PG) must NOT exceed 4ms.
N17E
FBVDDQ
POWER ON SEQUENCE POWER OFF SEQUENCE
GPPG0_PCH_PEXVDD_EN (GPP_G0) (PEX_VDD)
GPPG11_PCH_NVVDDS_EN (GPP_G11) (NVVDDS)
GPPG10_PCH_NVVDD_EN (GPP_G10) (NVVDD)
GPPG9_PCH_NV3V3_EN (GPP_G9) (NV3V3)
GPPG8_PCH_1V8RUN_EN (GPP_G8) (1V8_MAIN)
DGPU_PWR_EN (GPP_F23) (1V8_AON)
net PCH_GPIO Voltage
FBVDD/Q ON
NVVDDS OFF
Rt
2.6Amps @ 1.0V
Open VREG Type 0
PEX_VDD
Vout= Vref * (1+(Rt/Rb))
Rb
1.050V= 0.6 * (1+(7.5K/10K))
FBVDDQ_SENSE
FBVDDQ_SENSE_RTN
I2CC_SCL
I2CC_SDA
GPU_NVVDD_SENSE
GPU_GND_SENSE
PWR_SRC_VALID
SNN_TC
SNN_VPU
I2CC_SCL
I2CC_SDA
PWR_SRC_IMON_A0
PEX_VDD_R
PWR_SRC_WARN*
PWR_SRC_CRTCAL*
PS2_FBVDDQ_FB
10A 10A
0.400
PWR_SRC_VINNPWR_SRC_VINN_R
PWR_SRC_VINP_R
VIN2N
VIN2P
PWR_SRC_VINP
SNN_VIN3P
SNN_VIN3N
2.4A
PEX_VDD_R
1.1V
PS6_FB_MARGIN_PEXVDD
PS6_FB_RR_PEXVDD
0.400
4A
0.200
PEXVDD_EN
PEXVDD_EN
GND
5V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VIN
PWR_SRC_NV_FB
NV3V3
NV3V3
1V8_AON
VDD3
PEX_VDD
FBVDDQ_SENSE_RTN[28,64]
FBVDDQ_SENSE[28,64]
GPU_NVVDD_SENSE[28,62]
GPU_GND_SENSE[28,62]
NV_PEXVDD_EN [27]
PS2_FBVDDQ_FB[64]
I2CC_SCL [26,53]
VIN[10,35,39,50,54,55,56,57,58,59,60]
VDD3[5,26,30,31,32,33,34,35,37,38,48,49,50,51,52,54,56,59,60]
PEX_VDD[14,25]
NV3V3[11,12,13,14,26,46,52,61,62]
5V[39,44,45,48,49,50,51,52,54,55,56,57,58,59,63]
1V8_RUN[14,15,23,24,28,52]
3.3V[2,10,27,38,43,45,48,50,51,52,55,56]
PWR_SRC_NV_FB[61,62,64]
PWR_SRC_NV[62,63]
1V8_AON[3,23,24,26,27,28,31,52,61,62,64]
I2CC_SCL[26,53]
PWR_SRC_NVS_VINNP_R[61]
PWR_SRC_NVS_VINN_R[61]
PWR_SRC_NV_VINP_R[62]
PWR_SRC_NV_VINN_R[62]
GPIO28_OC_WARN# [26]
I2CC_SDA[26,53]
I2CC_SDA [26,53]
Title
Size Document Number Rev
Date: Sheet
of
6-71-PA700-D02A
D02A
[53] PEX_VDD
Custom
53 77Wednesday, Jul y 05, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-PA700-D02A
D02A
[53] PEX_VDD
Custom
53 77Wednesday, Jul y 05, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number Rev
Date: Sheet
of
6-71-PA700-D02A
D02A
[53] PEX_VDD
Custom
53 77Wednesday, Jul y 05, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
PR40 665K_1%_04
PR33 665K_1%_04
PR76 *160K_04
PC160
22u_6.3V_X5R_08
PR35 10_1%_04
PC42
0.01u_50V_X7R_04
PR30 10K_04
PC155
22u_6.3V_X5R_08
PC154
0.1u_10V_X7R_04
PR29 10_1%_04
PJ28
*3mm
1 2
PR75
10K_1%_04
S
D
G
Q5A
MTDK5S6R
2
61
PR271 0_04
PC43
10u_6.3V_X5R_06
PR41 10_1%_04
PC156
22u_6.3V_X5R_08
PR275 *10_1%_04
PC37
10u_6.3V_X5R_06
PR270 0_04
OpenVReg
PU9
EM5841BVT
1
FB
2
VCC
3
VIN
4
GND
5
GND
6
SW
7
SW
8
BOOT/NC
9
PGOOD
10
EN/FS
11
THERM
PR269
10_06
PC158 3300p_50V_X7R_04
S
D
G
Q5B
MTDK5S6R
5
34
PC57
0.1u_10V_X7R_04
INS16638818
PU1
INA3221AIRGV
1
VIN3N
2
VIN3P
3
GND
4
VS
5
A0
6
SCL
7
SDA
8
WARN
9
CRIT
10
PV
11
VIN1N
12
VIN1P
13
TC
14
VIN2N
15
VIN2P
16
VPU
17
PAD
PR42 10_1%_04
PR37 10K_04
PR38 665K_1%_04
R83
100K_04
PR273 10K_1%_04
R103
10_06
PC36
10u_6.3V_X5R_06
PRS2
RL1632T4F-B-R005-FNH
1
23
4
PL11
2.2uH_4*4*2.0
1 2
PR274 6.8K_1%_04
PR31 10_1%_04
PR28 0_04
PR32 10K_04
PC159
*0.1u_10V_X7R_04
PR34 0_04
PC157 *0.01u_16V_X 7R_04
PR36 10_1%_04
PC161
0.1u_10V_X7R_04
PR39
*10K_04
PR272 0_04
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