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Clevo PB50EF - Page 94

Clevo PB50EF
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
S0
S5/S4 S5/S4SusC
DD_ON
WLAN_PWR_EN
WLAN_EN
BT_EN
DD_ON and WLAN_PWR_EN , WLAN_EN , BT_EN signal between timing .
anywhere is Turn on or Turn off , it Timing tolerence is +- 1ms
point in BOT together
CLK_PCIEx_MINI
CLK_PCIEx_MINI
炲崘䶂枰怈暊
I/O
Trace(
USB
HDMI
D-SUB
DP
Headphone
MIC…
)
USB Trace
㚫ⷞ⇘
PCIE
䘬妲嘇ˤ
NCT3522U P/N: 6-02-03522-9C0
G5243A P/N: 6-02-05243-9C0
AP2821KTR-G1 P/N: 6-02-02821-9C0
Hybrid M.2 KEY-E 2230
WLAN
>40 mil
32KHz
The Hybrid M.2 E-Key is used for:
1. CNVi RF(Jefferson Peak)
2. Discrete WiFi (PCIe v2.1 Gen1)
3. CNVi+WiGig combo(Cedar Peak)
4. Qualcomm WiGig/WLAN/BT
combo(Sparrow) on Cannon Lake,
Coffee Lake, and Gemini Lake
platform.
BLUETOOTH
CNVi M.2 A+E KEY BT
USB 2.0 PORT
PCH-LP USB2.0 PORT-10
PCH-H USB2.0 PORT-14
USB
暨婳
BIOS
姕⭂
⭂䁢
XHCI
ᶵ⎗
⎗䓐
USB3.0 port
妲嘇
嘇㚫
㚫忈
忈ㆸ
BT Power Management Issue.
>40 mil
CNVi
WLAN+BT/CNVi
M:6-21-84KZ0-075
WLAN+BT/CNVi POWER
>120 mil>120 mil
PIN 72, 74
PIN 72, 74
20180410
follow common design
20180509
follow common design
PIN 2, 4
20180430
follow common design
20180430
follow common design
move 0.1u close to J_WLAN1
20180430
follow common design
MLCC Comm part
MLCC Comm part
20180502
Follow common design
close to PCH
close to M.2
close to M.2
close to M.2
close to M.2
20180509
Follow common design modify CNVi circuit
20180509
Follow common design
20180509
Follow common design
close to PCH
PIN 2, 4
20180521 RF check
20180521 RF check
20180716
Follow 0713 con list
20180803 Add
20180806
PCH use internal LDO
WLAN_3.3V
WLAN_3.3V
WLAN_3.3V
+V3.3A_V1.8A_VCCPGPPD
WLAN_3.3VVDD3
WLAN_3.3V
WLAN_3.3V
CNVI_BRI_RSP 35
CNVI_RGI_RSP 35
CLKIN_XTAL_LCP 40
CNVI_MFUART2_RXD 35
CNVI_GNSS_PA_BLANKING 35
USB_P1436
USB_P14#36
WLAN_EN 55
BT_EN 55
BUF_PLT_RST# 43,46,52,53,55,59,63
SUS_CLK 38
CNVI_RST# 38
CNVI_CLKREQ 38
CNVI_RGI_DT 35
CNVI_BRI_DT 35
CNVI_MFUART2_TXD 35
CNVI_WT_CLKP35
CNVI_WT_CLKN35
CNVI_WT_D0P35
CNVI_WT_D0N35
CNVI_WT_D1P35
CNVI_WT_D1N35
CLK_PCIE_WLAN40
PCIE_RXN16_WLAN37
PCIE_RXP16_WLAN37
PCIE_TXP16_WLAN37
PCIE_TXN16_WLAN37
CLK_PCIE_WLAN#40
WLAN_CLKREQ#40
CNVI_WR_CLKP35
CNVI_WR_CLKN35
CNVI_WR_D0P35
CNVI_WR_D0N35
CNVI_WR_D1P35
CNVI_WR_D1N35
CNVI_DET#55
WLAN_PWR_EN55
VDD34,10,29,31,34,35,36,37,38,41,43,46,52,53,55,57,58,64,65,66,67,68,69,71,72,74,77,78
CL_CLK1 37
CL_DATA1 37
CL_RST#1 37
CNVI_WAKE# 38
WLAN_W AKEUP#38
+V3.3A_V1.8A_VCCPGPPD35,41
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
07-03-2 M.2 WLAN+BT,CNVi
A3
45 91Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
07-03-2 M.2 WLAN+BT,CNVi
A3
45 91Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
Title
Size Document Number Rev
Date: Sheet
of
6-71-PB500-D03
D03
07-03-2 M.2 WLAN+BT,CNVi
A3
45 91Friday, December 07, 2018
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
PB50EF
R359 *0_04
R384 20K_04
R768 *0_04
R374 10K_04
R327 *33_04
U27
UP7553PMA5-25
EN
3
VIN
5
VIN/SS
4
VOUT
1
GND
2
C1501 0.1u_10V_X7R_04
T39
R767 *4.7K_04
R390 22_04
C1070
0.1u_6.3V_X5R_02
R402 71.5K_1%_04
R330 10K_04
C1507 0.1u_10V_X7R_04 R385 22_04
R326 10K_04
T40
R407 75K_1%_04
R336 *33_04
T88
E KEY
J_WLAN1
NFSE0-S6701-TP40
PCB Footprint = argosy_nfse0-s6701-tp64
P/N = 6-21-84KZ0-075
HEIGHT = 4.0mm
SUSCLK(32Khz)(O)
50
CLKREQ0_N
53
GND12
69
REFCLKP0
47
REFCLKN0
49
PEWAKE0_N
55
WT_D0N
65
WT_D0P
67
WT_D1N
59
WT_D1P
61
GND11
63
GND6
33
GND13
75
3.3V2
72
UART_CTS/RGI_RSP
34
I2C CLK(O)
60
UART_TX/RGI_DT
32
USB_DN
5
USB_DP
3
I2C DATA(IO)
58
COEX1_TXD(I/O)1.8V
48
PERST0_N(O)
52
COEX3(I/O)1.8V
44
GND10
57
LED2_N(OD)
16
3.3V0
2
CLINK_RESET
38
GND1
1
LED1_N(OD)
6
WGR_D0P
17
W_DISABLE1_N(O)
56
3.3V1
4
GND2
7
GND4
18
CLINK_DATA
40
GND7
39
PETP0
35
PERP0
41
PERN0
43
PETN0
37
GND8
45
GND9
51
IRQ_N(I)
62
COEX2_RXD(I/O)1.8V
46
3.3V3
74
GND5
19
WGR_CLKN
21
WGR_CLKP
23
UART_WAKE_N
20
UART_RX/BRI_RSP
22
UART_RTS/BRI_DT
36
CLINK_CLK
42
W_DISABLE2_N(O)
54
REFCLK0
64
PERST1_N
66
CLKREQ1_N
68
PEWAKE1_N
70
WT_CLKN
71
WT_CLKP
73
PCM_OUT/CLKREQ0
14
PCM_IN
12
PCM_SYNC/LCP_RSTN
10
PCM_CLK
8
WGR_D0N
15
GND3
13
WGR_D1P
11
WGR_D1N
9
C1157
1u_6.3V_X5R_02
R352 *0_04
R394 4.7K_04
R393 *0_04
R339 *33_04
R371 *0_04
C1155
22u_6.3V_X5R_06
T38
C1154
0.1u_6.3V_X5R_02
C1066
22u_6.3V_X5R_06
WLAN_EN
BT_EN
WLAN_PWR_EN
WLAN_3.3V
CNVI_BRI_RSP_R
CNVI_RGI_DT
CNVI_RGI_RSP_R
CNVI_BRI_DT
BUF_PLT_RST#
PCIE_TXP20_WLAN_R
PCIE_TXN20_WLAN_R
WLAN_EN
BT_EN
CNVI_RGI_DT
CNVI_BRI_DT
CNVI_WAKE#
WLAN_W AKEUP#
WLAN_W AKEUP#
Sheet 45 of 91
M.2 WLAN+BT
Schematic Diagrams
B - 46 M.2 WLAN+BT
B.Schematic Diagrams
M.2 WLAN+BT

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