Chapter 5 Input/Output Interfaces
5-2 Compaq Deskpro EN Series of Personal Computers
Desktop and Minitower Form Factors
Third Edition – September 1998
5.2.1.1 IDE Configuration Registers
The IDE controller is integrated into the south bridge (82371) component and configured as a
PCI device with bus mastering capability. The PCI configuration registers for the IDE controller
function (PCI device #20, function #1) are listed in Table 5-1.
Table 5–1
. IDE PCI Configuration Registers
Table 5-1.
EIDE PCI Configuration Registers (82371 Function 1)
PCI
Conf.
Addr. Register
Value
on
Reset
PCI
Conf.
Addr. Register
Value
on
Reset
00-01h Vender ID 8086h 24-3Fh Reserved
02-03h Device ID 7111h 40, 41h IDE Timing (Primary)
04-05h PCI Command 0000h 42, 43h IDE Timing (Secondary)
06-07h PCI Status 0000h 44h Slave IDE Timing
08h Revision ID 0Ah 45-47h Reserved
09h Programming 01h 48h UDMA Timing
0Ah Sub-Class 01h 49h Reserved
0Bh Base Class Code 80h 4A, 4Bh UDMA Timing
0Dh Master Latency Timer 0000h 4C-F7h Reserved
0Eh Header Type 80h F8-FBh Manufacturer’s ID
0F-1Fh Reserved 00h FC-FFh Reserved
20-23h BMIDE Base Address 00h -- -- --
NOTE:
Assume unmarked gaps are reserved and/or not used.
5.2.1.2 IDE Bus Master Control Registers
The IDE interface can perform PCI bus master operations using the I/O mapped control registers
listed in Table 5-2.
Table 5–2.
IDE Bus Master Control Registers
Table 5-2.
IDE Bus Master Control Registers
I/O Addr.
Offset
Size
(Bytes) Register
Default
Value
00h 2 Bus Master IDE Command (Primary) 00h
02h 2 Bus Master IDE Status (Primary) 00h
04h 4 Bus Master IDE Descriptor Ptr (Pri.) 0000 0000h
08h 2 Bus Master IDE Command (Secondary) 00h
0Ah 2 Bus Master IDE Status (Secondary) 00h
0Ch 4 Bus Master IDE Descriptor Ptr (Sec.) 0000 0000h
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