Computex FP-40 - ④ JTAG Interface

Technical Information on On-board Flash Programmer FP-40 Aug. 31, 2023 (Second edition)
9
④ JTAG interface
The signal table and target connection reference diagram when connecting a 20-pin 1.27mm pitch connector with JTAG
interface are shown below.
Signal table
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1 VTref Output 2 TMS
Input/
Output
3
GND
4
TCK
Input
5
GND
6
TDO
Output
7
Key
*3
8
TDI
Input
9
GND
10
SRST
*2
Input
11
GND
12
NC
13
GND
14
NC
Output
15
GND
16
TRST
*4
Input
17
GND
18
NC
19
GND
20
NC
*1: Input/output is denoted for the target system.
*2:
SRST is an open drain output signal.
Connect to the target system's "power-on reset" or "system reset"
with a wired OR circuit or, if a wired OR circuit is not possible, with
an OR circuit.
VCC should be connected to a power supply
matching the circuitry of the target system at 5 V or less.
*3: Intended for protection against erroneous insertion.
*4:
TRST is not used with Cortex-M core CPUs. Leave as NC. For
other CPUs, please refer to the datasheet of the CPU to be
connected.
Please note that CPUs that require connection may require the
signals to be pulled-down.
Note that some CPUs manufactured by Renesas Electronics require
some precautions. Refer to "Reference：RZ/A and RZ/T series
/SRST, /TRST reference diagram " below.
Target connection reference diagram
 To prevent malfunction, the length of wirings from the CPU to the target connector should be kept as short as possible.