Computex FP-40 - ⑥ JTAG Interface + Trace

Technical Information on On-board Flash Programmer FP-40 Aug. 31, 2023 (Second edition)
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⑥ JTAG interface + Trace
The signal table and target connection reference diagram when connecting a 10-pin 1.27mm pitch connector with JTAG
interface are shown below.
Signal table
Pin
No.
Signal
Input/
Output
*1
Pin
No.
Signal
Input/
Output
*1
1 Vtref Output 2 TMS
Input/
Output
3
GND
4
TCK
Input
5
GND
6
TDO
Output
7
Key
*3
8
TDI
Input
9
GND
10
SRSTn
*2
Input
*1
: Input/output is denoted for the target system.
*2
: Connect the reset signal to the connected CPU with a wired OR
circuit or an OR circuit. The SRSTn signal is an open collector
output.
*3
: Intended for protection against erroneous insertion.
Target connection reference diagram
 To prevent malfunction, the length of wirings from the CPU to the target connector should be kept as short as possible.
 If the waveform disturbance exceeds the device specifications, suppress the disturbance by inserting a damping resistor into the signal line or use
other means.