Coriant 8665 - NPU Subsystem; FPGA Subsystem; Timing Block

2 Line Unit (LU1)
PLD
Various system c on trol functio ns are embedded in HEP PLD.
I2C
I2C bus and switches are used for accessing devices such as EEPROMs, A/D converters and
temperature sensors.
RTC
The real time clock has backup for short power b r eaks. The tim e is kept for at least 20 hours (at
20º C/68º F).
A/D Converter
There is an analog -to -digital converter on the baseboard. It is used for measuring and monitori ng
operating voltages and temperatures.
Asynchronous RS-232 Serial Interface
The asynchronous serial interface is used for local m anagement connections.
External Alarm Interface
There is one dedicated general alarm output. There are also four alarm inputs.
2.3.2 NPU Subsystem
The N PU subsystem perform s layer 2 and layer 3 packet switching, packet forwarding, packet
filtering and traffic management functions. For data buffering and other functions, the NPU uses
DDR3 as well as TCAM memories.
2.3.3 FPGA Subsystem
The F PGA subsystem implem ents the timing logic for the timing block and m any miscellaneous
control functions.
2.3.4 Timing Block
The timing block is a Network Element Clock generator with a station clock interface. The
station clock interface supp orts a [G.703] 20 48 kHz synchronization interface or an interface with
Synchronization Status Messages.
The 8600 Smart Routers Network Element Clo ck complies with SEC [G.813] and Stratum 3
generator [GR-1244-CORE]. The functional modelling is specified in [ETS 300 4 17-6-1] an d
[G.781].
76.8670-40128B 8600 Smart Rou ters
© 2015 Coriant. 8665 Smart Router FP7.0 Reference Manual
31