Corvalent Q77AX - Page 59

59
► PE3 Slot Configuration
PE2 Slot
Disabled or Enabled
ASPM Support
Disabled, L0s, L1, LosL1 or Auto
URR
Disabled or Enabled
FER
Disabled or Enabled
NFER
Disabled or Enabled
CER
Disabled or Enabled
CTO
Disabled or Enabled
SEFE
Disabled or Enabled
SENFE
Disabled or Enabled
SECE
Disabled or Enabled
PME SCI
Disabled or Enabled
Hot Plug
Disabled or Enabled
PCIe Speed
Auto, Gen1 or Gen2
Extra Bus Reserved
0
Reserved Memory
10
Reserved I/O
4
► Mini PCIE Slot Configuration
Mini PCIE Support
Disabled or Enabled
ASPM Support
Disabled or Enabled
URR
Disabled or Enabled
FER
Disabled or Enabled
NFER
Disabled or Enabled
CER
Disabled or Enabled
CTO
Disabled or Enabled
SEFE
Disabled or Enabled
SENFE
Disabled or Enabled
SECE
Disabled or Enabled
PME SCI
Disabled or Enabled
Hot Plug
Disabled or Enabled
PCIe Speed
Auto, Gen1 or Gen 2