MA-5002VZ Service Manual
4-6 Circuit Theory
130446-1 Rev. A
©2000 Crown International, Inc.
U702A. S700, physically accessible from behind the
front grille, determines the VZ operating mode. In high
voltage mode (Q42930-0 Control Module only) the out-
put of U702A is held low. This in turn keeps the 555
output high and the MOSFETs are kept on. In the high
current mode, U702A is held in the opposite polarity,
keeping the output of the 555 low and the MOSFETs off.
In the AUTO position of S700, the audio level sense
circuitry controls the threshold and reset inputs to the
555. The 555 will then switch states to high voltage when
the audio level is sufficient and will switch back down
automatically when level has dropped sufficiently. Ca-
pacitors in the U705 circuitry control the speed of the
down-shift. In the VZ-ODEP mode, the switch operates
as it would in AUTO mode unless ODEP limiting is in
progress. When ODEP limiting occurs, optic coupler
U704 pulls the reset control low to the 555 to turn the
MOSFET switches off, and keep them off (low voltage/
high current mode) until the ODEP limiting condition
clears.
Upstream of the toroids are the soft-start and protec-
tion mechanisms used to power down the amplifier.
Although tied into the power supply primary, these cir-
cuits are covered in Section 4.6, Protection Systems.
The low voltage power supply utilizes a separate trans-
former. The front panel power switch and a 1A fuse
(F702) are the only components upstream of this trans-
former. The output of the rectifier produces ±24VDC
unregulated. U715 and U716 produce regulated
±15VDC respectively. (A separate fullwave rectifier pro-
duces pulsed DC for Over-voltage sense and Soft-start
control.)
4.4 ODEP Theory
To protect the output stages from adverse thermal con-
ditions, a specially developed “ODEP” (Output Device
Emulator Protection) circuit is used. It produces a com-
plex analog output signal proportional to the always
changing safe-operating-area (SOA) margin of the out-
put transistors. This output signal controls the Voltage
Translator stage and Low Side output stage bias. This
action removes only the drive that may exceed the safe-
operating-area of the output stage.
Thermal sensors give the ODEP circuitry vital informa-
tion on the operating temperature of the heat sinks on
which the output devices are mounted. This tempera-
ture signal combines with the complex ODEP signal to
form the heart of our patented ODEP protection scheme.
4.4.1 ODEP Operation
Refer to Figure 4.4 for a diagram of the basic operation
of the ODEP system.
The ODEP circuitry actually comes in two parts, one
positive and the other negative. For the purposes of
this discussion, only the channel 1 ODEP circuitry is
covered here, and the focus will primarily be on the
positive half.
An LM-334Z thermal sensor provides a calibrated out-
put from the output modules. At 25°C its output is 2.98V,
with a 10 mV increase per every 1°C rise in heatsink
temperature.
This thermal sensor output, from the positive sensor,
goes to three destinations. First is a buffer which drives
the calibrated temperature test point at pin 7 of TP1/
TP2. Second is an over-temperature limit trip (thermal
limit amplifier, as shown below). This will cause both
the positive and the negative ODEP circuit to go into,
and remain in, hard ODEP until the heatsinks cool. Third,
it goes down into a circuit which combines thermal and
output power information.
The thermal sensor from the negative output module
only performs this last function.
A pair of sense lines from the Low Side emitter resistors
provide current information. Combined with VCC infor-
mation, actual instantaneous power is calculated. A
combining circuit determines the net thermal condition
based on the power being delivered for the existing
heat level. The ODEP amplifier accepts this input infor-
mation and, using an RC model of the heat transfer
characteristics of the output devices (as mounted in
the heatsinks), creates a complex output proportional
to the thermal reserve of the output devices.
Output from the positive ODEP amplifier ranges from
– 12V (cold) to +9V (hard ODEP). This output drives the
positive LS bias feed control circuit (see Section 4.2.2)
and the negative HS Voltage Translator feed control cir-
cuit (see Section 4.5.2). Also, this circuit provides test
point monitoring information and VZ-ODEP VZ mode
control information.
Output from the negative ODEP amplifier ranges from
+12V (cold) to – 9V (hard ODEP). This output drives the
negative LS bias feed control circuit (see Section 4.2.2)
and the positive HS Voltage Translator feed control cir-
cuit (see Section 4.5.2). Also, this circuit provides test
point monitoring information, VZ-ODEP control informa-
tion, and front panel ODEP (thermal reserve) LED con-
trol information.
Also tapping into the ODEP output control of LS bias
feed and Voltage Translator feed are signals from the
fault, power (turn-on delay), and power loss (brown-
out) circuits. By using the output of ODEP for ±LL and
±LH control, these sources can mute the audio to the
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