dCS Delius User Manual Manual for Software Issue 2.3x
dCS Ltd September 2004
Manual filename: Delius Manual v2.3x.doc Page 48 email: more@dcsltd.co.uk
English version web-site: www.dcsltd.co.uk
Volume Control
• Digitally implemented, 0 to –60dB in 0.5dB steps
Balance Control
• Digitally implemented, 0 to –40dB in variable steps, each side.
• Mutes one channel at minimum settings.
De-Emphasis
• Auto-selected, 50/15µs, CCITT J17 or none, available at 32, 44.1 or 48kS/s.
Analogue Outputs
Balanced Unbalanced
Type
Balanced,
not floating
Single ended,
ground referred
Source impedance
(20Hz-20kHz)
< 1Ω + 100µH< 1Ω + 100µH
Maximum load 600 600
Ω
Noise, unweighted
(20Hz-20kHz)
< -110 < -105 dB0
Spurious responses
(20Hz-20kHz)
< -100 < -100 dB0
L-R crosstalk,
(20Hz-20kHz)
< -90 < -90 dB
Level for full scale
(set by the Out menu)
6 or 2 6 or 2 V rms
Connectors XLR male (2) RCA Phono (2)
Connections +Signal on pin 2
-Signal on pin 3
-
Table 6 – Analogue Output Electrical Characteristics
Clocking
The sample clock quality significantly determines the output performance of the
converter. The highest quality clocks that are available are crystals, so we use
these. Delius uses two on-board voltage controlled crystal oscillators (VCXO’s)
as clock sources - one for the 44.1kS/s related outputs and one for the 48kS/s
related outputs.
Only one VCXO is active at a time. In slave mode, the active VCXO is
synchronised to the clock signal extracted from the input by a phase locked loop
(PLL). This PLL is of a special narrow bandwidth type, that provides a
significant degree of "clock cleaning”. The PLL is also very robust, and will lock
to very poor signals if necessary. Data is decoded using a much wider band
(faster) PLL, so AES3 type low frequency jitter on the input clock can be
handled, and will be cleaned.
Synchronising to source x
Pull-in range ± 300 ppm about nominal frequency
Lock-in time < 6 seconds for most situations
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