Denon AVR-X3000 - Page 165

165
W9864G6JH-6 Block diagram
W9864G2IH
Publication Release Date: Aug. 28, 2009
- 6 - Revision A03
6. BLOCK DIAGRAM
DQ0
DQ31
DQM0~3
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 2048 * 256 * 32
ROW DECODER
ROW DECODER ROW DECODERROW DECODER
A0
A9
BS0
BS1
CS
RAS
CAS
WE