Eaton EDR-5000 - Page 1009

EDR-5000 IM02602007E
Name Description
Logic.LE42.Out Signal: Latched Output (Q)
Logic.LE42.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE43.Gate Out Signal: Output of the logic gate
Logic.LE43.Timer Out Signal: Timer Output
Logic.LE43.Out Signal: Latched Output (Q)
Logic.LE43.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE44.Gate Out Signal: Output of the logic gate
Logic.LE44.Timer Out Signal: Timer Output
Logic.LE44.Out Signal: Latched Output (Q)
Logic.LE44.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE45.Gate Out Signal: Output of the logic gate
Logic.LE45.Timer Out Signal: Timer Output
Logic.LE45.Out Signal: Latched Output (Q)
Logic.LE45.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE46.Gate Out Signal: Output of the logic gate
Logic.LE46.Timer Out Signal: Timer Output
Logic.LE46.Out Signal: Latched Output (Q)
Logic.LE46.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE47.Gate Out Signal: Output of the logic gate
Logic.LE47.Timer Out Signal: Timer Output
Logic.LE47.Out Signal: Latched Output (Q)
Logic.LE47.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE48.Gate Out Signal: Output of the logic gate
Logic.LE48.Timer Out Signal: Timer Output
Logic.LE48.Out Signal: Latched Output (Q)
Logic.LE48.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE49.Gate Out Signal: Output of the logic gate
Logic.LE49.Timer Out Signal: Timer Output
Logic.LE49.Out Signal: Latched Output (Q)
Logic.LE49.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE50.Gate Out Signal: Output of the logic gate
Logic.LE50.Timer Out Signal: Timer Output
Logic.LE50.Out Signal: Latched Output (Q)
Logic.LE50.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE51.Gate Out Signal: Output of the logic gate
Logic.LE51.Timer Out Signal: Timer Output
Logic.LE51.Out Signal: Latched Output (Q)
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