Eaton EDR-5000 - Page 324

EDR-5000 IM02602007E
Name Description
Logic.LE28.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE29.Gate Out Signal: Output of the logic gate
Logic.LE29.Timer Out Signal: Timer Output
Logic.LE29.Out Signal: Latched Output (Q)
Logic.LE29.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE30.Gate Out Signal: Output of the logic gate
Logic.LE30.Timer Out Signal: Timer Output
Logic.LE30.Out Signal: Latched Output (Q)
Logic.LE30.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE31.Gate Out Signal: Output of the logic gate
Logic.LE31.Timer Out Signal: Timer Output
Logic.LE31.Out Signal: Latched Output (Q)
Logic.LE31.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE32.Gate Out Signal: Output of the logic gate
Logic.LE32.Timer Out Signal: Timer Output
Logic.LE32.Out Signal: Latched Output (Q)
Logic.LE32.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE33.Gate Out Signal: Output of the logic gate
Logic.LE33.Timer Out Signal: Timer Output
Logic.LE33.Out Signal: Latched Output (Q)
Logic.LE33.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE34.Gate Out Signal: Output of the logic gate
Logic.LE34.Timer Out Signal: Timer Output
Logic.LE34.Out Signal: Latched Output (Q)
Logic.LE34.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE35.Gate Out Signal: Output of the logic gate
Logic.LE35.Timer Out Signal: Timer Output
Logic.LE35.Out Signal: Latched Output (Q)
Logic.LE35.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE36.Gate Out Signal: Output of the logic gate
Logic.LE36.Timer Out Signal: Timer Output
Logic.LE36.Out Signal: Latched Output (Q)
Logic.LE36.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE37.Gate Out Signal: Output of the logic gate
Logic.LE37.Timer Out Signal: Timer Output
Logic.LE37.Out Signal: Latched Output (Q)
Logic.LE37.Out inverted Signal: Negated Latched Output (Q NOT)
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