Eaton EDR-5000 - Page 327

EDR-5000 IM02602007E
Name Description
Logic.LE56.Out Signal: Latched Output (Q)
Logic.LE56.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE57.Gate Out Signal: Output of the logic gate
Logic.LE57.Timer Out Signal: Timer Output
Logic.LE57.Out Signal: Latched Output (Q)
Logic.LE57.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE58.Gate Out Signal: Output of the logic gate
Logic.LE58.Timer Out Signal: Timer Output
Logic.LE58.Out Signal: Latched Output (Q)
Logic.LE58.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE59.Gate Out Signal: Output of the logic gate
Logic.LE59.Timer Out Signal: Timer Output
Logic.LE59.Out Signal: Latched Output (Q)
Logic.LE59.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE60.Gate Out Signal: Output of the logic gate
Logic.LE60.Timer Out Signal: Timer Output
Logic.LE60.Out Signal: Latched Output (Q)
Logic.LE60.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE61.Gate Out Signal: Output of the logic gate
Logic.LE61.Timer Out Signal: Timer Output
Logic.LE61.Out Signal: Latched Output (Q)
Logic.LE61.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE62.Gate Out Signal: Output of the logic gate
Logic.LE62.Timer Out Signal: Timer Output
Logic.LE62.Out Signal: Latched Output (Q)
Logic.LE62.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE63.Gate Out Signal: Output of the logic gate
Logic.LE63.Timer Out Signal: Timer Output
Logic.LE63.Out Signal: Latched Output (Q)
Logic.LE63.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE64.Gate Out Signal: Output of the logic gate
Logic.LE64.Timer Out Signal: Timer Output
Logic.LE64.Out Signal: Latched Output (Q)
Logic.LE64.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE65.Gate Out Signal: Output of the logic gate
Logic.LE65.Timer Out Signal: Timer Output
Logic.LE65.Out Signal: Latched Output (Q)
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