Eaton EDR-5000 - Page 982

EDR-5000 IM02602007E
Name Description
IRIG-B.Control Signal6 Signal: IRIG-B Control Signal
IRIG-B.Control Signal7 Signal: IRIG-B Control Signal
IRIG-B.Control Signal8 Signal: IRIG-B Control Signal
IRIG-B.Control Signal9 Signal: IRIG-B Control Signal
IRIG-B.Control Signal10 Signal: IRIG-B Control Signal
IRIG-B.Control Signal11 Signal: IRIG-B Control Signal
IRIG-B.Control Signal12 Signal: IRIG-B Control Signal
IRIG-B.Control Signal13 Signal: IRIG-B Control Signal
IRIG-B.Control Signal14 Signal: IRIG-B Control Signal
IRIG-B.Control Signal15 Signal: IRIG-B Control Signal
IRIG-B.Control Signal16 Signal: IRIG-B Control Signal
IRIG-B.Control Signal17 Signal: IRIG-B Control Signal
IRIG-B.Control Signal18 Signal: IRIG-B Control Signal
SNTP.SNTP active Signal: If there is no valid SNTP signal for 120 sec, SNTP is regarded as inactive.
Statistics.ResFc all Signal: Resetting of all Statistic values (Current Demand, Power Demand, Min, Max)
Statistics.ResFc I Demand Signal: Resetting of Statistics - Current Demand (avg, peak avg)
Statistics.ResFc P Demand Signal: Resetting of Statistics - Power Demand (avg, peak avg)
Statistics.ResFc Max Signal: Resetting of all Maximum values
Statistics.ResFc Min Signal: Resetting of all Minimum values
Statistics.StartFc I Demand-I State of the module input: Start of Statistics of the Current Demand (Update the displayed Demand )
Statistics.StartFc P Demand-I State of the module input: Start of Statistics of the Active Power Demand
Logic.LE1.Gate Out Signal: Output of the logic gate
Logic.LE1.Timer Out Signal: Timer Output
Logic.LE1.Out Signal: Latched Output (Q)
Logic.LE1.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE1.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE1.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE1.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE2.Gate Out Signal: Output of the logic gate
Logic.LE2.Timer Out Signal: Timer Output
Logic.LE2.Out Signal: Latched Output (Q)
Logic.LE2.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE2.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE2.Gate In3-I State of the module input: Assignment of the Input Signal
www.eaton.com 982