Eaton EDR-5000 - Page 992

EDR-5000 IM02602007E
Name Description
Logic.LE39.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE39.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE40.Gate Out Signal: Output of the logic gate
Logic.LE40.Timer Out Signal: Timer Output
Logic.LE40.Out Signal: Latched Output (Q)
Logic.LE40.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE40.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE40.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE40.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE40.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE40.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE41.Gate Out Signal: Output of the logic gate
Logic.LE41.Timer Out Signal: Timer Output
Logic.LE41.Out Signal: Latched Output (Q)
Logic.LE41.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE41.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE41.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE41.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE41.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE41.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE42.Gate Out Signal: Output of the logic gate
Logic.LE42.Timer Out Signal: Timer Output
Logic.LE42.Out Signal: Latched Output (Q)
Logic.LE42.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE42.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE42.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE42.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE42.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE42.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE43.Gate Out Signal: Output of the logic gate
Logic.LE43.Timer Out Signal: Timer Output
Logic.LE43.Out Signal: Latched Output (Q)
Logic.LE43.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE43.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE43.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE43.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE43.Gate In4-I State of the module input: Assignment of the Input Signal
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