Eaton EDR-5000 - Page 994

EDR-5000 IM02602007E
Name Description
Logic.LE48.Gate Out Signal: Output of the logic gate
Logic.LE48.Timer Out Signal: Timer Output
Logic.LE48.Out Signal: Latched Output (Q)
Logic.LE48.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE48.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE48.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE48.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE49.Gate Out Signal: Output of the logic gate
Logic.LE49.Timer Out Signal: Timer Output
Logic.LE49.Out Signal: Latched Output (Q)
Logic.LE49.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE49.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE49.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE49.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE50.Gate Out Signal: Output of the logic gate
Logic.LE50.Timer Out Signal: Timer Output
Logic.LE50.Out Signal: Latched Output (Q)
Logic.LE50.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE50.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE50.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE50.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE50.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE50.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE51.Gate Out Signal: Output of the logic gate
Logic.LE51.Timer Out Signal: Timer Output
Logic.LE51.Out Signal: Latched Output (Q)
Logic.LE51.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE51.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE51.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE51.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE51.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE51.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE52.Gate Out Signal: Output of the logic gate
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