Eaton EDR-5000 - Page 997

EDR-5000 IM02602007E
Name Description
Logic.LE60.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE60.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE60.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE60.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE60.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE60.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE61.Gate Out Signal: Output of the logic gate
Logic.LE61.Timer Out Signal: Timer Output
Logic.LE61.Out Signal: Latched Output (Q)
Logic.LE61.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE61.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE61.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE61.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE61.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE61.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE62.Gate Out Signal: Output of the logic gate
Logic.LE62.Timer Out Signal: Timer Output
Logic.LE62.Out Signal: Latched Output (Q)
Logic.LE62.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE62.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE62.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE62.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE62.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE62.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE63.Gate Out Signal: Output of the logic gate
Logic.LE63.Timer Out Signal: Timer Output
Logic.LE63.Out Signal: Latched Output (Q)
Logic.LE63.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE63.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE63.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE63.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE63.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE63.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE64.Gate Out Signal: Output of the logic gate
Logic.LE64.Timer Out Signal: Timer Output
Logic.LE64.Out Signal: Latched Output (Q)
Logic.LE64.Out inverted Signal: Negated Latched Output (Q NOT)
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