Eaton EDR-5000 - Page 999

EDR-5000 IM02602007E
Name Description
Logic.LE68.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE68.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE68.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE68.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE69.Gate Out Signal: Output of the logic gate
Logic.LE69.Timer Out Signal: Timer Output
Logic.LE69.Out Signal: Latched Output (Q)
Logic.LE69.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE69.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE69.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE69.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE69.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE69.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE70.Gate Out Signal: Output of the logic gate
Logic.LE70.Timer Out Signal: Timer Output
Logic.LE70.Out Signal: Latched Output (Q)
Logic.LE70.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE70.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE70.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE70.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE70.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE70.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE71.Gate Out Signal: Output of the logic gate
Logic.LE71.Timer Out Signal: Timer Output
Logic.LE71.Out Signal: Latched Output (Q)
Logic.LE71.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE71.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE71.Gate In2-I State of the module input: Assignment of the Input Signal
Logic.LE71.Gate In3-I State of the module input: Assignment of the Input Signal
Logic.LE71.Gate In4-I State of the module input: Assignment of the Input Signal
Logic.LE71.Reset Latch-I State of the module input: Reset Signal for the Latching
Logic.LE72.Gate Out Signal: Output of the logic gate
Logic.LE72.Timer Out Signal: Timer Output
Logic.LE72.Out Signal: Latched Output (Q)
Logic.LE72.Out inverted Signal: Negated Latched Output (Q NOT)
Logic.LE72.Gate In1-I State of the module input: Assignment of the Input Signal
Logic.LE72.Gate In2-I State of the module input: Assignment of the Input Signal
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