Epson EPL-5500 - Page 130

A.1.1 Main Board (C169 MAIN-B Board)
Table A-2. CN2 Pin Assignments
Pin No. Signal Name I/O Description
1
Vss
—
Ground
2
DQ0
I/O
Data bus bit 0
3
DQ16
I/O
Data bus bit 16
4
DQ1
I/O
Data bus bit 1
5
DQ17
I/O
Data bus bit 17
6
DQ2
I/O
Data bus bit 2
7
DQ18
I/O
Data bus bit 18
8
DQ3
I/O
Data bus bit 3
9
DQ19
I/O
Data bus bit 19
10
Vcc
—
+5 VDC
11
NC
—
Not connected
12
MA0
O
Memory address bit 0
13
MA1
O
Memory address bit 1
14
MA2
O
Memory address bit 2
15
MA3
O
Memory address bit 3
16
MA4
O
Memory address bit 4
17
MA5
O
Memory address bit 5
18
MA6
O
Memory address bit 6
19
MA10
O
Memory address bit 10
20
DQ4
I/O
Data bus bit 4
21
DQ20
I/O
Data bus bit 20
22
DQ5
I/O
Data bus bit 5
23
DQ21
I/O
Data bus bit 21
24
DQ6
I/O
Data bus bit 6
25
DQ22
I/O
Data bus bit 22
26
DQ7
I/O
Data bus bit 7
27
DQ23
I/O
Data bus bit 23
28
MA7
O
Memory address bit 7
29
NC
—
Not connected
30
Vcc
—
+5 VDC
31
MA8
O
Memory address bit 8
32
MA9
O
Memory address bit 9
33
RAS3
O
RAS 3
34
RAS2
O
RAS 2
35
MP2
—
Not used
36
MP0
—
Not used
37
MP1
—
Not used
38
MP3
—
Not used
39
Vss
—
Ground
40
CAS0
O
CAS 0
41
CAS2
O
CAS 2
42
CAS3
O
CAS 3
43
CAS1
O
CAS 1
44
RAS0
O
RAS 0
45
RAS1
O
RAS 1
46
NC
—
Not connected
47
WE
O
Write enable
48
NC
—
Not connected
49
DQ8
I/O
Data bus bit 8
Appendix EPL-5500 Service Manual
A-4 Rev. A