REV.-A
2.3.2 Reset Circuit
The control circuits are initialized when the RESET signal is issued. The reset operation occurs under these
two conditions:
(1) Power on reset
Immediately after the power is turned on, +35
VDC
is rapidly generated. Because it takes a moment for the
voltage at ZD2 to reach +31.5 V, the voltage at the DISC terminal on the gate array does not reach +5
VDC
until capacitor
C24
is fully charged. A similar integration circuit is provided in the gate array and further
delays the output of the ROUT signal. This low level is used as a reset signal.
(2)
INIT signal reset
The reset signal is also issued when the
INIT signal is sent from the host computer.
Figure 2-25 shows the power on reset circuit.
GA
(IC4)
+35VDC
+5VDC
+
4
RIN
DISC ROUT
‘D2~
D7
~R31
P’-’’--5’
R80
i
C24
I
R79
L
55 15
d
CPU (IC2CI) 15
RESET
Figure 2-25. Power On Reset Circuit
2-25
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