Epson LQ-1170 - Printhead Drive Circuit

REV.-A
2.3.6 Printhead Drive Circuit
Figure 2-24 shows the printhead drive circuit in block diagram form. The print data already has been
expanded to create the image data. The CPU splits up this data three times and transfers this information
to the latch circuit in the
E05A49. The CPU samples the voltage of the +35 V line via the A/D converter.
(See section 2.3.3.) The CPU outputs a pulse via the CPU time output port
PPO. The length of this pulse
corresponds to the +35 V line voltage. This pulse becomes the head drive signal. In this way, PU4 135
(8 A-1 3A) outputs head drive signals (signals HD 1 to HD24) that relate to voltage levels through the
length of the pulses. These signals are output to the head for each of the sections of print data that
were created by dividing the data three times before sending it.
By sampling the +35 V line voltage and determining the length of the head drive signal, it is possible
to keep the energy supplied to the head constant. If the voltage of the +35 V line is HIGH, the CPU
shortens the output pulse. If the voltage of the +35 V line is LOW, the CPU lengthens the output pulse.
Figure 2-25 shows the timing of the head drive signal output.
E05A49 (4B) PU4135 (8 -1 3A)
HEAD 1-24
B 1-4 X6
Switching
–
+35V
PPO
Q8.Q 1-6
Cl- 6
HD1-24
~
Printhead
CPU
— TH
— REFERENCE
4.741 v
P50
I
DATA LINE
I
I I , D7A
1
I
I 11 / -1
I 3.3K 1 %
Figure 2-24.
Printhead Drive Circuit
E05A49
output
PU4‘1 35
Cl -C6
HD1-24
r
----------
r
-----------—
I I
I
1
L ----------l
L . ----------A
Figure 2-25. Head Drive Signal Output Timing
2-21