Chapter 4. Software framework
• When using ash, you need to pay attention to its service life. As ash can sustain only a limited
number of erase operations, you need to plan and manage the usage of ash. For example, you can
use wear leveling to extend the service life of ash.
• It should be noted that writing operations to ash occupy CPU resources, which may inuence the
system response time. As a result, the writing operation to ash should be avoided as much as
possible.
What kind of sectors are reserved for customized use in ESP8266 modules?
• For previous versions of SDK rel3.0, besides for bootloader and app bin, the following sectors are reserved
at the end of the congured ash: 1 for system information, 1 for OTA information and 1 for RF calibration
information.
• For SDK rel3.0 and later versions, we use partition_table to manage ash. Except for partition_table and
bootloader, other bin les are all marked in partition_table.
How to read ash data for ESP8266?
• You can use the script tool under ESP8266-RTOS-SDK to read ash data. The whole process is shown as
follows:
– Install python environment and the required packages;
– Go to ESP8266_RTOS_SDK/components/esptool_py/esptool;
– Run python esptool.py --chip esp8266 --port /dev/ttyUSB0 --baud 115200
read_flash 0x0 0x400000 esp8266.bin. In this command,“esp8266.bin”is a self-dened
le, where all ash data read will be stored;“/dev/ttyUSB0”is the serial port number in linux environment,
which can be dierent in other environments and systems.
Why do dierent ESP32 modules have inconsistent ash erase times?
• Dierent ESP32 modules may have dierent ash chips or ash controllers, which may aect the erase time.
Some models of ash do not have a mechanism to skip empty blocks during erasing, so it takes longer time.
Specically, dierent ash chips may have dierent erase time, for example, the erase time of SPI ash and
QSPI ash is dierent. Even the same type of ash chip may have dierent erase time as they are produced and
packaged in dierent batches. In addition, the design and performance of the ash controller may also aect
the erase time. Therefore, erase time varies in ESP32 modules with dierent ash chips and ash controllers.
When the ash SPI mode is set to QIO mode on the ESP32-S3-WROOM-2-32R8V module, the running
rmware prints the following error. Why?
E (47) qio_mode: Failed to set QIE bit, not enabling QIO mode
The ESP32-S3-WROOM-2-32R8V module uses the 32 MB Octal ash and the 8 MB Octal PSRAM.
Please enable the settings in the conguration options:
• (Top) > Serial flasher config > [*] Enable Octal Flash > Flash SPI
mode (OPI)
• (Top) > Component config > ESP PSRAM > Support for external,
SPI-connected RAM > SPI RAM config > Mode (QUAD/OCT) of SPI RAM
chip in use
Espressif Systems 114
Submit Document Feedback
Release master
To Next Page
Loading...
Need help?
General