Chapter 2. Development environment
2.2.10 ESP8266 enters boot mode (2,7) and hits a watchdog reset. What could be wrong?
• Please make sure that when ESP8266 boots, the strapping pins are held in the required logic levels. If externally
connected peripherals drive the strapping pins to an inappropriate logic level, ESP8266 may boot into a wrong
mode of operation. With the absence of a valid program, the WDT may then reset the chip.
• Thus, in design practices, it is recommended to only use the strapping pins for input to high resistive external
devices so that the strapping pin is not forced high/low at power-up. For more information, please refer to
ESP8266 Boot Mode Selection.
2.2.11 When using the ESP-WROVER-KIT board with OpenOCD, an error occurred
as: Can’t nd board/esp32-wrover-kit-3.3v.cfg. How can I resolve such issue?
• With 20190313 and 20190708 versions of OpenOCD, please use instruction openocd -f board/
esp32-wrover.cfg.
• With 20191114 and 20200420 (2020 later versions) versions of OpenOCD, please use instruction openocd
-f board/esp32-wrover-kit-3.3v.cfg.
2.2.12 The RTC_watch_dog keeps resetting during ESP32 SPI boot. What could be the
reason?
• Reason: The ash has a requirement for time interval between VDD_SDIO power-up and the rst access. For
example, GD’s 1.8 V ash requires 5 ms of time interval, while the time interval of ESP32 is about 1 ms
(XTAL frequency is 40 MHz). Under such condition, the ash access will fail and either timer watchdog reset
or RTC watchdog reset is triggered, depending on which one is triggered rst. The threshold for RTC watchdog
reset is 128 KB cycle, while the threshold for timer watchdog reset is 26 MB cycle. Taking the 40 MHz XTAL
clock as an example, when the frequency of RTC slow clock is greater than 192 KHz, an RTC watchdog reset
will be triggered rst, otherwise a timer watchdog reset will be triggered. VDD_SDIO will be continuously
powered when the timer watchdog is reset, so there will be no problem in accessing ash and the chip will work
normally. When the RTC watchdog is reset, the VDD_SDIO power supply will be disabled and the access to
ash will fail, resetting the RTC_watch_dog continuously.
• Solution: When an RTC watchdog reset occurs, the power supply to VDD_SDIO is disabled. You can add a
capacitor to VDD_SDIO to ensure that the voltage of VDD_SDIO does not drop below the voltage that the
ash can tolerate during this period.
2.2.13 How to obtain and parse coredump with ESP32?
• To obtain the 64 KB coredump le from the rmware, you need to know its oset from the partition
table. Assuming the oset is 0x3F0000, run the following command to read the rmware:
python esp-idf/components/esptool_py/esptool/esptool.py -p /dev/ttyUSB*␣
,→read_flash 0x3f0000 0x10000 coredump.bin
• Use the coredump reading script to convert the le obtained at the rst step into readable messages.
Assuming the coredump le is coredump.bin and the elf le is hello_wolrd.elf, run the following
command to convert the le:
python esp-idf/components/espcoredump/espcoredump.py info_corefile -t raw␣
,→-c coredump.bin hello_world.elf
For more information, please refer to the Core Dump documentation.
Espressif Systems 12
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