Revision B MAC™ 5000 resting ECG analysis system 2-7
2024917-010
Equipment Overview: Theory of Operation
Atmel AT91RM9200 CPU Containing:
Incorporates the ARM920T™ ARM® Thumb™ Processor
- 200 MIPS at 180 MHz, Memory Management Unit
- 16-KByte Data Cache, 16-KByte Instruction Cache,
Write Buffer
- In-circuit Emulator including Debug Communication
Channel
- Mid-level Implementation Embedded Trace Macrocell
(256-ball BGA Package Only)
Low Power: 30.4 mA on VDDCORE, 3.1 mA in Standby Mode
Additional Embedded Memories
- 16K Bytes of SRAM and 128K Bytes of ROM
External Bus Interface (EBI)
- Supports SDRAM, Static Memory, Burst Flash, Glueless
Connection to CompactFlash®, SmartMedia
™ and
NAND Flash
System Peripherals for Enhanced Performance:
- Enhanced Clock Generator and Power Management
Controller
- Two On-chip Oscillators with Two PLLs
- Very Slow Clock Operating Mode and Software Power
Optimization Capabilities
- Four Programmable External Clock Signals
- System Timer Including Periodic Interrupt, Watchdog and
Second Counter
- Real-time Clock with Alarm Interrupt
- Debug Unit, Two-wire UART and Support for Debug
Communication Channel
- Advanced Interrupt Controller with 8-level Priority,
Individually Maskable Vectored Interrupt Sources, Spurious
Interrupt Protected
- Seven External Interrupt Sources and One Fast Interrupt
Source
- Four 32-bit PIO Controllers with Up to 122 Programmable
I/O Lines, Input Change Interrupt and Open-drain
Capability on Each Line
- 20-channel Peripheral Data Controller (DMA)
Multimedia Card Interface (MCI)
- Automatic Protocol Control and Fast Automatic Data
Transfers
- MMC and SD Memory Card-compliant, Supports Up to Two
SD Memory Cards
Three Synchronous Serial Controllers (SSC)
- Independent Clock and Frame Sync Signals for Each
Receiver and Transmitter
- I 2 S Analog Interface Support, Time Division Multiplex
Support
- High-speed Continuous Data Stream Capabilities with 32-bit
Data Transfer
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