Appendix B - Settings and Signals
ORDINAL SIGNAL NAME ELEMENT NAME
DESCRIPTION
Output DDB can be applied to inhibit reclose by adjacent scheme until local autoreclose scheme confirms it is OK to close CB
Single Phase AR reclaim time running
DDB_SP_RECLAIM_TIME_COMPLETE
Single Phase AR reclaim time complete
Three Phase AR reclaim time running
DDB_TP_RECLAIM_TIME_COMPLETE
Three Phase AR reclaim time complete
This signal is set when CB has successfully completed a single phase autoreclose cycle.
DDB_CB_FAST_SYSTEM_CHECK_OK
OK to reclose CB with sync check without waiting for dead time to complete
DDB_CB_LEADER_SYSTEM_CHECK_OK
System conditions OK to reclose CB when dead time complete
DDB_CB_MANUAL_SYSTEM_CHECK_OK
System conditions OK to manually close CB
DDB_CB_FAIL_PROTECTION_TRIP
signal to force CB AR lockout
Line-Bus slip freq > setting [48 93] (frequency difference (slip) between line voltage and bus voltage is greater than maximum slip permitted
for CB synchronism check type 1)
Line-Bus slip freq < setting [48 93] (frequency difference (slip) between line voltage and bus voltage is greater than maximum slip permitted
for CB synchronism check type 1)
Line Volts < setting [48 8B]
Line Volts > setting [48 8C]
Bus Volts < setting [48 8B]
Bus Volts > setting [48 8C]
DDB_SYSCHECKS_VLINE_DIFF_HIGH
Voltage magnitude difference between Line V and Bus V is greater than setting [48 91] (line V > Bus V)
DDB_SYSCHECKS1_2_VLINE_DIFF_HIGH
Voltage magnitude difference between Line V and Bus V is greater than setting [48 96] (line V > Bus V)
DDB_SYSCHECKS_VBUS_DIFF_HIGH
Voltage magnitude difference between Line V and Bus V is greater than setting [48 91] (line V < Bus V)
DDB_SYSCHECKS1_2_VBUS_DIFF_HIGH
Voltage magnitude difference between Line V and Bus V is greater than setting [48 96] (line V < Bus V)
DDB_CS1_LINE_FREQ_GT_BUS_FREQ
Frequency difference between Line V and Bus V is greater than setting [48 93] (line freq > Bus freq)
DDB_CS1_LINE_FREQ_LT_BUS_FREQ
Frequency difference between Line V and Bus V is greater than setting [48 93] (line freq < Bus freq)
Line/Bus phase angle in range: setting [48 90] to +180deg (anticlockwise from Vbus)
Line/Bus phase angle in range: setting [48 90] to -180deg (anticlockwise from Vbus)
Line freq > (Bus freq + 0.001Hz) (Line voltage vector rotating anticlockwise relative to VBus1)
Bus freq > (Line freq + 0.001Hz) (Line voltage vector rotating clockwise relative to VBus1)
External input via DDB to enable CB, if "in service", to be initiated for autoreclosing by an AR initiation signal from protection. DDB input
defaults to high if not mapped in PSL, so CB AR initiation is permitted.
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