HackRF
(continued from previous page)
# CLKIN_DIV=0 (Divide by 1)
# PLLB_SRC=0 (XTAL input)
# PLLA_SRC=0 (XTAL input)
[0xC0 15 0x00]
# Registers 16 through 23: CLKx Control
# CLK0:
# CLK0_PDN=0 (powered up)
# MS0_INT=1 (integer mode)
# MS0_SRC=0 (PLLA as source for MultiSynth 0)
# CLK0_INV=0 (not inverted)
# CLK0_SRC=0 (XTAL as clock source for CLK0)
# CLK0_IDRV=3 (8mA)
[0xC0 16 0x43 0x80 0x80 0x80 0x80 0x80 0x80 0x80]
# Enable CLK0 output only.
[0xC0 3 0xFE]
Clocking Scheme (Work In Progress)
From AN619: If Fxtal=25MHz, Fvco = Fxtal * (a + (b / c)). If we want Fvco = 800MHz, a = 32, b = 0, c = don’t care.
MSNA_P1[17:0] = 128 * a + floor(128 * b / c) - 512
= 128 * a + floor(0) - 512
= 128 * 32 + 0 - 512
= 3584 = 0xE00
MSNA_P1[17:16] (register 28) = 0x00
MSNA_P1[15: 8] (register 29) = 0x0E
MSNA_P1[ 7: 0] (register 30) = 0x00
MSNA_P2[19:0] = 128 * b - c * floor(128 * b / c)
= 128 * 0 - 0 * floor(128 * 0 / X)
= 0
MSNA_P3[19:0] = 0
MultiSynth0 should output 40MHz (800MHz VCO divided by 20):
a = 20, b = 0, c = X
MS0_P1[17: 0] = 128 * a + floor(128 * b / c) - 512
= 2048 = 0x800
MS0_P1[17:16] (register 44) = 0x00
MS0_P1[15: 8] (register 45) = 0x08
MS0_P1[ 7: 0] (register 46) = 0x00
MS0_P2[19:0] = 0
MS0_P3[19:0] = 0
MultiSynth1 should output 20MHz (800MHz VCO divided by 40) or some smaller integer fraction of the VCO:
a = 40, b = 0, c = X
MS1_P1[17: 0] = 128 * a + floor(128 * b / c) - 512
= 4608 = 0x1200
MS1_P1[17:16] (register 52) = 0x00
(continues on next page)
24.1. Si5351 I2C 91
To Next Page
Loading...