Hitachi HDS721050CLA362 - Table 30 Device Control Register; Data Register

HITACHI Deskstar & CinemaStar 7K1000.B & Deskstar E7K1000 Hard Disk Drive specification
47
In LBA Mode this register contains Bits 8-15. At the end of the command, this register is updated to reflect the
current LBA Bits 8-15.
The cylinder number may be from zero to the number of cylinders minus one.
When 48-bit addressing commands are used, the "most recently written" content contains LBA Bits 8-15, and
the "previous content" contains Bits 32-39.
8.5 Data Register
This register is used to transfer data blocks between the device data buffer and the host. It is also the register
through which sector information is transferred on a Format Track command, and configuration information is
transferred on an Identify Device command.
All data transfers are 16 bits wide, except for ECC byte transfers, which are 8 bits wide. Data transfers are PIO
only.
The register contains valid data only when DRQ=1 in the Status Register.
8.6 Device Control Register
Device Control Register
7
6
5
4
3
2
1
0
HOB
-
-
-
1
SRST
-IEN
0
Table 29 Device Control Register
Bit Definitions
HOB
HOB (high order byte) is defined by the 48-bit Address feature set. A write to
any Command Register shall clear the HOB bit to zero.
SRST (RST)
Software Reset. The device is held reset when RST=1. Setting RST=0
reenables the device.
The host must set RST=1 and wait for at least 5 microseconds before setting
RST=0, to ensure that the device recognizes the reset.
-IEN
Interrupt Enable. When -IEN=0, and the device is selected, device interrupts to
the host will be enabled. When -IEN=1, or the device is not selected, device
interrupts to the host will be disabled.