Chapter 1 Hardware Structure
33
V
D D
M
U
X
R e a d D a t a R e g i s t e r
D
Q
C K
S
D
Q
C K
Q
S
C o n t r o l B i t
P u l l - H i g h O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
Q
I
2
C C o n f i g u r a t i o n O p t i o n
P A 6 / S D A , P A 7 / S C L
( e x c e p t H T 4 6 R 4 7 / H T 4 6 C 4 7 )
M
U
X
T o I
2
C C i r c u i t
T o I
2
C C i r c u i t
M
U
X
W a k e - u p O p t i o n
S y s t e m W a k e - u p
W e a k
P u l l - u p
PA6/SDA, PA7/SCL Input/Output Ports
V
D D
M
U
X
R e a d D a t a R e g i s t e r
D
Q
C K
S
D
Q
C K
S
C o n t r o l B i t
P u l l - H i g h O p t i o n
D a t a B u s
W r i t e C o n t r o l R e g i s t e r
C h i p R e s e t
R e a d C o n t r o l R e g i s t e r
W r i t e D a t a R e g i s t e r
D a t a B i t
P B 0 / A N 0 ~ P B 7 / A N 7
( H T 4 6 R 4 7 / H T 4 6 C 4 7 w i t h
P B 0 / A N 0 ~ P B 3 / A N 3 o n l y )
Q
Q
A C S 2 ~ A C S 0
T o A / D C o n v e r t e r
A n a l o g
I n p u t
S e l e c t o r
P C R 2
P C R 1
P C R 0
W e a k
P u l l - u p
PB Input/Output Ports