Holtek HT66F30 - Page 190

Rev. 2.50 190 June 22, 2017 Rev. 2.50 191 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
SPI Communication
AftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,when
dataiswrittentotheSIMDregister,transmission/receptionwillbeginsimultaneously.Whenthe
datatransferiscomplete,theTRFflagwillbesetautomatically,butmustbeclearedusingthe
applicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,
anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedinto
theSIMDregister.ThemastershouldoutputanSCSsignaltoenabletheslavedevicebeforea
clocksignalisprovided.Theslavedatatobetransferredshouldbewellpreparedattheappropriate
momentrelativetotheSCSsignaldependinguponthecongurationsoftheCKPOLBbitandCKEG
bit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignal
forvariouscongurationsoftheCKPOLBandCKEGbits.
TheSPIwillcontinuetofunctionevenintheIDLEMode.
  
 
    
   
   
   
 
 

  
       
       
    
SPI Master Mode Timing
 
 


  
       
   
    
SPI Slave Mode Timing – CKEG=0