Rev. 2.50 244 June 22, 2017 Rev. 2.50 245 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Bit2 TXBRK:Transmitbreakcharacter
0:Nobreakcharacteristransmitted
1:Breakcharacterstransmit
TheTXBRKbitistheTransmitBreakCharacterbit.Whenthisbitis0,thereare
nobreakcharactersandtheTXpinoperatesnormally.Whenthebitis1,thereare
transmitbreakcharactersandthetransmitterwillsendlogiczeros.Whenthisbitis
equalto1,afterthebuffereddatahasbeentransmitted,thetransmitteroutputisheld
lowforaminimumofa13-bitlengthanduntiltheTXBRKbitisreset.
Bit1 RX8:Receivedatabit8for9-bitdatatransferformat(readonly)
Thisbitisonlyusedif9-bitdatatransfersareused,inwhichcasethisbitlocationwill
storethe9thbitofthereceiveddataknownasRX8.TheBNObitisusedtodetermine
whetherdatatransfersarein8-bitor9-bitformat.
Bit0 TX8:Transmitdatabit8for9-bitdatatransferformat(writeonly)
Thisbitisonlyusedif9-bitdatatransfersareused,inwhichcasethisbitlocation
willstorethe9thbitofthetransmitteddataknownasTX8.TheBNObitisusedto
determinewhetherdatatransfersarein8-bitor9-bitformat.
UCR2 register
TheUCR2registeristhesecondoftheUARTcontrolregistersandservesseveralpurposes.One
ofitsmainfunctionsistocontrolthebasicenable/disableoperationiftheUARTTransmitterand
ReceiveraswellasenablingthevariousUARTinterruptsources.Theregisteralsoservestocontrol
thebaudratespeed,receiverwake-upfunctionenableandtheaddressdetectfunctionenable.
Furtherexplanationoneachofthebitsisgivenbelow:
Bit 7 6 5 4 3 2 1 0
Name TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE
R/W R/W R/W R/W R/W R/W R/W R W
POR 0 0 0 0
1 0 1 1
Bit7 TXEN:UARTTransmitterenablecontrol
0:UARTtransmitterisdisabled
1:UARTtransmitterisenabled
ThebitnamedTXENistheTransmitterEnableBit.Whenthisbitisequalto0,the
transmitterwillbedisabledwithanypendingdatatransmissionsbeingaborted.In
additionthebufferswillbereset.InthissituationtheTXpinwillbeinthestateof
highimpedance.IftheTXENbitisequalto1andtheUARTENbitisalsoequalto
1,thetransmitterwillbeenabledandtheTXpinwillbecontrolledbytheUART.
ClearingtheTXENbitduringatransmissionwillcausethedatatransmissiontobe
abortedandwillresetthetransmitter.Ifthissituationoccurs,theTXpinwillbeinthe
stateofhighimpedance.
Bit6 RXEN:UARTReceiverenablecontrol
0:UARTreceiverisdisabled
1:UARTreceiverisenabled
ThebitnamedRXENistheReceiverEnableBit.Whenthisbitisequalto0,the
receiverwillbedisabledwithanypendingdatareceptionsbeingaborted.Inaddition
thereceivebufferswillbereset.InthissituationtheRXpinwillbeinthestateofhigh
impedance.IftheRXENbitisequalto1andtheUARTENbitisalsoequalto1,the
receiverwillbeenabledandtheRXpinwillbecontrolledbytheUART.Clearingthe
RXENbitduringareceptionwillcausethedatareceptiontobeabortedandwillreset
thereceiver.Ifthissituationoccurs,theRXpinwillbeinthestateofhighimpedance.