Rev. 2.50 246 June 22, 2017 Rev. 2.50 247 June 22, 2017
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
HT66F20/HT66F30/HT66F40/HT66F50/HT66F60
HT66FU30/HT66FU40/HT66FU50/HT66FU60
A/D Flash MCU with EEPROM
Bit5 BRGH:BaudRatespeedselection
0:Lowspeedbaudrate
1:Highspeedbaudrate
ThebitnamedBRGHselectsthehighorlowspeedmodeoftheBaudRateGenerator.
Thisbit,togetherwiththevalueplacedinthebaudrateregisterBRG,controlsthe
BaudRateoftheUART.Ifthisbitisequalto1,thehighspeedmodeisselected.Ifthe
bitisequalto0,thelowspeedmodeisselected.
Bit4 ADDEN:Addressdetectfunctionenablecontrol
0:Addressdetectfunctionisdisabled
1:Addressdetectfunctionisenabled
ThebitnamedADDENistheaddressdetectfunctionenablecontrolbit.Whenthis
bitisequalto1,theaddressdetectfunctionisenabled.Whenitoccurs,ifthe8th
bit,whichcorrespondstoRX7ifBNO=0orthe9thbit,whichcorrespondstoRX8
ifBNO=1,hasavalueof1,thenthereceivedwordwillbeidentiedasanaddress,
ratherthandata.Ifthecorrespondinginterruptisenabled,aninterruptrequestwillbe
generatedeachtimethereceivedwordhastheaddressbitset,whichisthe8thor9th
bitdependingonthevalueofBNO.Iftheaddressbitknownasthe8thor9thbitofthe
receivedwordis0withtheaddressdetectfunctionbeingenabled,aninterruptwillnot
begeneratedandthereceiveddatawillbediscarded.
Bit3 WAKE:RXpinfallingedgewake-upfunctionenablecontrol
0:RXpinwake-upfunctionisdisabled
1:RXpinwake-upfunctionisenabled
Thisbitenablesordisablesthereceiverwake-upfunction.Ifthisbitisequalto1and
theMCUisinIDLEorSLEEPmode,afallingedgeontheRXinputpinwillwake-up
thedevice.Ifthisbitisequalto0andtheMCUisinIDLEorSLEEPmode,anyedge
transitionsontheRXpinwillnotwake-upthedevice.
Bit2 RIE:Receiverinterruptenablecontrol
0:Receiverrelatedinterruptisdisabled
1:Receiverrelatedinterruptisenabled
Thisbitenablesordisablesthereceiverinterrupt.Ifthisbitisequalto1andwhen
thereceiveroverrunagOERRorreceivedataavailableagRXIFisset,theUART
interruptrequestagwillbeset.Ifthisbitisequalto0,theUARTinterruptrequest
agwillnotbeinuencedbytheconditionoftheOERRorRXIFags.
Bit1 TIIE:TransmitterIdleinterruptenablecontrol
0:Transmitteridleinterruptisdisabled
1:Transmitteridleinterruptisenabled
Thisbitenablesordisablesthetransmitteridleinterrupt.Ifthisbitisequalto1and
whenthetransmitteridleagTIDLEisset,duetoatransmitteridlecondition,the
UARTinterruptrequestagwillbeset.Ifthisbitisequalto0,theUARTinterrupt
requestagwillnotbeinuencedbytheconditionoftheTIDLEag.
Bit0 TEIE:TransmitterEmptyinterruptenablecontrol
0:Transmitteremptyinterruptisdisabled
1:Transmitteremptyinterruptisenabled
Thisbitenablesordisablesthetransmitteremptyinterrupt.Ifthisbitisequalto1and
whenthetransmitteremptyagTXIFisset,duetoatransmitteremptycondition,the
UARTinterruptrequestagwillbeset.Ifthisbitisequalto0,theUARTinterrupt
requestagwillnotbeinuencedbytheconditionoftheTXIFag.