HP 3465B - Page 16

Section IV
Model 3465B
This logic level is sensed by the logic section to determine
polarity and zero-detect.
4-25. Auto-Zero Circuit. During the measurement se
quence, the auto-zero loop is closed except for the run-up
and run-down intervals. This loop includes the slope
amplifier and the integrator but does not physically include
the input amplifier although the loop does compensate for
the input amplifier offset. When the auto-zero loop is
closed, the input of the input amplifier is grounded. If the
summation of currents at the integrator summing junction
is not zero, the integrator begins to ramp up for a negative
summation or ramp down for a positive summation. The
integrator output is applied through the X4000 slope
amplifier to the auto-zero capacitor, C4. The voltage on the
auto-zero capacitor causes a current to flow at the summing
Junction that returns the summation to zero. This auto-zero
configuration compensates for the analog offset of the
input amplifier and integrator by providing a current at the
summing junction that cancels the currents resulting from
the offset.
4-26. Logic Section.
4-27. The Logic Section is comprised of combinational and
state logic. This section processes the comparator output to
determine the polarity of the input signal and to make a
voltage—to—time conversion of the input signal. Time
accumulated during the conversion is proportional to the
input signal and is stored. The display is derived from this
accumulated time. A voltage-to-time conversion with the
accumulated time being stored occurs once each measure
ment sequence.
4-28. Seven blocks make up the logic section. These blocks
are:
a. Clock
b. State Clock
c. Polarity and Zero Detect
d. Data Transfer and Reset
e. Control State Counter
f. Control State Decode
g. Data Accumulator
The HIGH and LOW logic levels used in the logic section
are 0 V and - 7 V respectively. The following discussion
describes the basic operation of the logic section.
4-29. Clock and State Clock. The timing of the logic
section is derived from the clock circuit. The clock operates
at 100 kHz and is crystal-controlled. A state clock, driven
by the clock output and the count extend line from the
data accumulator, drives the control state counter to
initiate each measurement interval.
4-30. Polarity and Zero Detect. The polarity and zero-
detect circuit monitors the comparator output. The state of
this output at the beginning of the run-down interval
determines the polarity of the input signal. Zero-detect is
determined at the point the comparator output changes
states during the run-down, overrange or overflow intervals.
If the integrator ramps positive (negative input signal)
during run-up, the comparator output goes HIGH and
returns to LOW at the zero-detect point. If the integrator
ramps negative (positive input signal) during run-up, the
comparator output goes low and returns to high at the
zero-detect point. These comparator output logic states are
stored in a D flip—flop. At the beginning of the run-down
interval, this state identifies the polarity of the input signal.
The outputs of the D flip—flop provide the signals needed
to select the correct polarity display and the correct
reference supply signal (11, 12) during the run-down
interval. An EXCLUSIVE OR and latch processes the
comparator output to provide the zero-detect signal.
4-31. Data Transfer and Reset. The data transfer and reset
circuits provide logic signals to the data accumulator
required to load the storage latches and reset the decade
counters. A detailed description of the data accumulator is
provided in the detailed theory section. While the TXFR
input of the data accumulator is low, data in the decade
counters is transferred to the static storage latches. The
RESET input resets the decade counters to zero when low.
This must occur after the transfer to the storage latches has
taken place. To ensure that reset occurs after termination
of transfer, an RC delay circuit precedes the reset gates.
4-32. Control State Counter. The control state counter
provides the timing for the measurement sequence intervals.
The output from the counter establishes the timing of the
analog control signals (IZ, 10, 11 and 12) which are applied
to the A—D converter. The state clock and reset inputs to
the control state counter determine the outputs of the
counter.
4-33. Control State Decode. The control state decode
converts the polarity, zero-detect and control state counter
inputs to the correct analog control signals. These signals,
applied to the A—D converter, perform the measurement
sequence switching. This switching consists of the input
amplifier switch, the auto-zero switch and the reference
supply switches.
4-34. Data Accumulator. The data accumulator consists of
a counter, data latches, a multiplexer, digit select decoder
and output buffers. At the beginning of the Run-Down
interval of the measurement sequence, the data accumula
tor begins to count clock pulses until zero-detect occurs.
This count is proportional to the input signal and is the
time conversion used to generate the display. The digit
select decoder scans the display digits from the most
significant digit to the least significant digit while the
multiplexer provides the corresponding BCD outputs for
each digit. A detailed discussion of the data accumulator is
presented in the detailed theory.
4-35. Display.
4-36. The multimeter display contains four full digits with
an overrange "1" and polarity sign. All segments and indi
cators are light-emitting diodes. A BCD-to-seven segment
decoder receives BCD information from the data accumu-
4-4