HP 3465B - Page 54

Model 3465B
Section VII
7-37. Display and Display Driver Verification and Trouble
shooting Test.
7-38. This test should be performed in addition to the
quick test to check the display and display driver. The test
is also used for troubleshooting between the display driver
and display LED inputs. Implement the test as follows:
a. Connect the test point — 7 and test point LT
located on the A2 display interface board.
b. Verify display. If all drivers and LED's are function
ing properly, the display will appear as follows:
b. Verify the following signals:
i u u u
I I
NOTE
Position of the decimal point will be dependent
on the range selected.
If the display is not realized, the failure can be determined
by symptoms and the use of Schematic 3. If the fault is
corrected, return the ANALOG/DIGITAL ISOLATION
JUMPER to its original position (connect test point COM?
to CP).
7-39. Place the ANALOG/DIGITAL ISOLATION
JUMPER from test point CP to test point PL. Place the
front panel controls in the following positions:
POWER ON
FUNCTION DC Volts
RANGE 200 m
The first indication that the digital and display section is
functioning properly will be a front panel display of
I I I
POLARITY
ALTERNATING
with the plus/minus indicator alternating at a 1.25 Hz rate.
In the event that this verification or any of the following
verifications fail, normal digital troubleshooting techniques
in conjunction with Schematic 3 should be used to isolate
and correct the failure.
7-40. Polarity, Zero Detect and Clock Circuit Verification.
7-41. Maintain the ANALOG/DIGITAL ISOLATION
JUMPER connection between test points CP and PL with
FUNCTION and RANGE settings at DCV and 200 m
respectively.
a. Verify the 100 kHz clock at test point CL.
TEST
POINTS
PL
400 ms ■
TC
RS
200 ms
0
•APPROXIMATELY 100 fis PULSE
If the PL, TC and RS signals are present, the polarity, zero
detect and clock circuits are verified.
7-42. Analog Switch Lines and Control State Counter
Verification.
7-43. Maintain the ANALOG/DIGITAL ISOLATION
JUMPER connection between test points CP and PL with
FUNCTION and RANGE settings at DCV and 200 m
respectively. Verify the following signals:
SIGNAL
10
(U9 PIN 3)
11
(US PIN 10)
12
(US PIN 9)
n
I
SOO ms
IZ
(U6 PIN
n,TJ U LT
0
-7
0
-7
0
-7
0
-7
•1 TO 6 MS PULSE
If verification of the 10, II, 12 and IZ signals is made, the
analog switch lines and control state counter are function
ing.
7-44. Data Accumulator Input/Output Verification.
7-45. Maintain the ANALOG/DIGITAL ISOLATION
JUMPER connection between test points CP and PL with
FUNCTION and RANGE settings at DCV and 200 m
respectively. Perform the following steps.
7-5