HP 4262A - Page 239

Section VIII
A14 BOARD CIRCUIT DESCRIPTION.
PHASE
LOCKED
LOOP
(PLL)
CIRCUIT
AND
4
PHASE
GENERATOR.
Figure
C
shows
the
block
diagram
of
the
phase
locked
loop
circuit
used
to
establish
an
accurate
detection
phase
in
the
phase
detector.
The
PLL
technique
was
incorporated
to
develop
an
input
to
the
Four
Phase
Generator
which
satisfies
the
requirements
of
phase
and
frequency
aceuracies
for
establishing
the
exact
relationships
between
the
four
phase
generator
output
and
the
measurement
signal.
When
the
PLL
control
is
off,
the
VCO
oscillates
at
a
frequency
close
to
40
times
the
fre-
quency
of
the
input
signal
(€ref)
to
the
Phase
Shifter.
In
the
120Hz
measurement
setting,
the
frequency
of
VCO
output
becomes
4.8kHz.
A
1/10
down
counter
U15
and
the
Four
Phase
Generator
Ul2
(a
1/4
down
counter)
count
down
the
VCO
output
frequency
to
120Hz.
This
becomes
the
fre-
quency
of
the
feedback
signal
@f
to
the
local
phase
detector
(LPD)
U9.
The
output
voltage
of
the
LPD
(converted
to
a dec
by
Low
Pass
Filter
Q7
and
Q8)
directs
the
oscillation
of
VCO
so
that
the
differ-
ence
in
both
frequency
and
phase
between
the
two
input
signals
(@ref
and
€f)
to
the
LPD
tends
to
become
minimum.
Eventually,
both
the
phase
and
frequency
of
the
four
phase
generator
output
(one
of
four)
is
precisely
the
same
as
that
of
the
€ref
signal
(120Hz).
In
a
1kHz
measurement
frequency
setting,
switch
Q9
is
turned
off
to
change
the
oscil-
lation
frequency
of
the
VCO
to
40kHz.
In
a
manner
similar
to
that
for
the
120Hz
measurement,
the
four
phase
generator
output
is
fixed
to
the
exact
frequency
of
€ref
signal
(1kHz).
When
measurement
frequency
is
switched
to
10kHz,
the
40kHz
VCO
output
passes
through
the
gate
cir-
cuitry
(U14)
and
bypasses
the
1/10
down
counter.
Thus,
the
frequency
of
the
feedback
signal
ef
Model 4262A
becomes
10kHz.
The
frequency
of
the
four
phase
generator
input
is
always
four
times
the
€ref
signal
frequency.
The
4f
pulse
train
is
converted
to
four
square
wave
signals,
each
having
an
exact
phase
difference
of
0°,
90°,
180°
and
270°
with
respect
to
the
negative
edge
of
the
€ref
signal.
The
U13
Gate
circuitry
periodically
creates
a
short
pulse
which
drives
sampling
switch
(Q5)
of
the
period
averaging
circuit
in
synchronism
with
the
measurement
signal.
In a 10kHz measurement, the four phase generator
output is fed to the 1/10 down counter whose
output
is
inputted
to
gate
circuitry
U13.
The
U13
output is a Imsec (1kHz) pulse train which drives
the sampling switch Q5 at a rate of once in 20
periods of the period averaging circuit input (phase
detector output) signal. The periodic rate is
sufficient for period averaging of the high fre-
quency input signal.
INTEGRATOR NULL OFFSET CONTROL.
During
the
offset
null
sequence
period,
the
Ampli-
fier
output
offset
voltages
present
in
the
phase
detector
and
the
integrator
stages
are
reduced
to
zero
at
the
integrator
output.
While
the
offset
null
is
being
performed,
switches
A13Q18
and
Q19
interrupt
€m
signal
transfer
to
the
Phase
Detector.
Simultaneously,
A14Q1
and
Q2
turm
on.
Q2
provides
the
integrator
with
a
lower
input
resis-
tance
and
advances
charging
to
achieve
a
shorter
null
offset
control
period.
The
Integrator
produces
a
dc
output
which
represents
the
accumulated
charge
of
the
offset
voltages.
The
integrator
output
is
stored
in
capacitor
C1
to
maintain
its
voltage
during
the
measurement
cycle.
Any
incoming
voltage
to
the
integrator
is
referenced
to
the
voltage
across
the
charged
capacitor.
Thus,
any
offset
voltages
present
are
eliminated
and
are
not
a
factor
in
the
integrator
output.
Phase
Detector
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T
ue | T i | ]GENERATOR g ::fig J";/2
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L o averaging
_ circuit QS
In a 10kHz measurement,
active switches U13 and
U14 change their states.
Figure
C.
Phase
Locked
Loop
Circuit
Block
Diagram.
8-56 .
-~