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S:\HP8924C\USRGUIDE\BOOK\chapters\hpibstat.fb
Chapter 4, Status Reporting
Status Reporting
In the Test Set, the Transition Filters are implemented as two registers: a 16-bit
positive transition (PTR) register and a 16-bit negative transition (NTR) register.
A positive transition of a bit in the Condition register will be latched in the Event
Register if the corresponding bit in the positive transition filter is set to 1. A
positive transition of a bit in the Condition register will not be latched in the Event
Register if the corresponding bit in the positive transition filter is set to 0. A
negative transition of a bit in the Condition register will be latched in the Event
Register if the corresponding bit in the negative transition filter is set to 1. A
negative transition of a bit in the Condition register will not be latched in the
Event Register if the corresponding bit in the negative transition filter is set to 0.
Either transition (PTR or NTR) of a bit in the Condition Register will be latched in
the Event Register if the corresponding bit in both transition filters is set to 1. No
transitions (PTR or NTR) of a bit in the Condition Register will be latched in the
Event Register if the corresponding bit in both transition filters is set to 0.
Transition Filters are read-write. Transition Filters are unaffected by a *CLS
(clear status) command or queries. The Transitions Filters are set to pass positive
transitions (PTR) at power on and after receiving the *RST (reset) command (all
16 bits of the PTR register set to 1 and all 16 bits of the NTR register set to 0).
Event Register
The Event Register captures bit-state transitions in the Condition Register as
defined by the Transition Filters. Each bit in the Event Register corresponds to a
bit in the Condition Register, or if there is no Condition Register/Transition Filter
combination, each bit corresponds to a specific condition in the Test Set. Bits in
the Event Register are latched, and, once set, they remain set until cleared by a
query of the Event Register or a *CLS (clear status) command. This guarantees
that the application can’t miss a bit-state transition in the Condition Register.
There is no buffering; so while an event bit is set, subsequent transitions in the
Condition Register corresponding to that bit are ignored. Event Registers are read-
only. Event Registers in the Test Set are either 8 or 16 bits long and may contain
unused bits. All unused bits return a zero value when read.
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