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3-5 SCOPE CIRCUITS
3-5-1 SCOPE RECEIVER CIRCUIT (SCOPE UNIT)
A portion of the 64.455 MHz 1st IF signal from the 1st mixer
circuit (RXPLL-A/B units; IC1051, Q1211, Q1212: while
receiving) or IF amplifier (MAIN unit; Q506: while transmit-
ting) passes through the switches (IC1, IC31). The switched
signal is passed through the PIN attenuator (D1, D2), low-
pass filter (L13, L14, C42–C46) and bandpass filter (L5, L6,
C11–C13, C41) and then amplified at the IF amplifiers (Q2).
The amplified signal is mixed with the 18.455–20.455 MHz
scope 2nd LO (S2LO) signal at the mixer circuit (D101) to
produce the 45 MHz IF signal. The mixed IF signal is passed
through the ceramic bandpass filter (FI201) to suppress
unwanted signals. The filtered IF signal is applied to other
mixer (D4) after amplifying at 2 amplifiers (Q201, Q202).
The signal is applied to the amplifier (IC401, pin 6), and then
passes through the low-pass filter (IC403, pins 1, 6). The fil-
tered signal is amplified at the amplifier (IC404, pin 6), and
is then applied to the DSP IC (IC601) via the A/D converter
(IC501, pin 43). The DSP IC analyzes digital signals, and
then outputs digital data to the CPU.
3-5-2 SCOPE UNIT AGC CIRCUIT (SCOPE UNIT)
A pert of the filtered signal at the low-pass filter (IC403, pin
1) is applied to the amplifier (IC404, pin 6). The amplified
signal is applied to the AGC detector (D401, D402), and is
then applied to the AGC amplifier (IC405, pin 2). The ampli-
fied signal is applied to the comparator section to compare
with “ATTV” signal. The signal is amplified at the AGC ampli-
fier (Q1), and is then applied to the PIN attenuator (D1, D2)
to keep same gain.
3-5-3 SWEEP LO CIRCUIT (SCOPE UNIT)
The 40 MHz signal is applied to the J3 from the RXPLL-B
unit. The signal is used for reference system clock of each
circuits.
(1) S2 LO CIRCUIT
The 40 MHz reference system clock is amplified at the
amplifiers (Q701 and Q720). The amplified signal is applied
to the 14 bits DDS IC (IC820, pin 62). The DDS IC which is
controlled by the CPU outputs 19.555 MHz (for MAIN RX) or
19.555±0.5 MHz (for SUB RX) system clock from pin 45,
and then passes through the low-pass filter (L761–L763,
C761–C767), high-pass filter (L764, C768–C770) and atten-
uator (R764–R766). The attenuated signal is applied to the
LO amplifier (Q101), and then passes through the low-pass
filter (L104, C108–C110) and attenuator (R105–R107). The
attenuated signal is applied to the mixer circuit (D101) as S2
LO signal (19.555–20.455 MHz).
(2) S3 LO CIRCUIT
The 40 MHz reference system clock is amplified at the
amplifiers (Q701, Q810). The amplified signal is applied to
the PLL IC (IC801, pin 8). The applied signal passes through
the 1/400 divider and phase detector circuits of the IC, and
is then applied to the VCO circuit (Q821) via the loop filter to
produce 44.8 MHz signal. The 44.8 MHz signal is amplified
at the buffer amplifiers (Q841–Q843), and then passes
through the low-pass filter (L851, L852, C852–C856) to sup-
press high-harmonics components. The filtered signal pass-
es through the attenuator (R856–R858), and is then ampli-
fied at the amplifier (Q301). The signal passes through the
other attenuator (R302–R304), and is then applied to the
mixer circuit (D4) as S3 LO signal.
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