PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAMx32_2.fm - Rev. J 12/08 EN
9 ©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
Pin/Ball Assignments and Descriptions
Table 4: Pin/Ball Descriptions
86-Pin TSOP
Numbers
90-Ball VFBGA
Numbers Symbol Type Description
68 J1 CLK Input
Clock: CLK is driven by the system clock. All SDRAM input signals
are sampled on the positive edge of CLK. CLK also increments
the internal burst counter and controls the output registers.
67 J2 CKE Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the
CLK signal. Deactivating the clock provides PRECHARGE power-
down and SELF REFRESH operation (all banks idle), ACTIVE
power-down (row active in any bank), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except
after the device enters power-down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during
power-down and self refresh modes, providing low standby
power. CKE may be tied HIGH.
20 J8 CS# Input
Chip select: CS# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when CS# is registered HIGH, but READ/WRITE bursts
already in progress will continue and DQM operation will retain
its DQ mask capability while CS# is HIGH. CS# provides for
external bank selection on systems with multiple banks. CS# is
considered part of the command code.
17, 18, 19 K8, K7, J9 WE#,
CAS#,
RAS#
Input
Command inputs: WE#, CAS#, and RAS# (along with CS#)
define the command being entered.
16, 71, 28, 59 K9, K1, F8, F2 DQM0–
DQM3
Input
Input/output mask: DQM is sampled HIGH and is an input
mask signal for write accesses and an output enable signal for
read accesses. Input data is masked during a WRITE cycle. The
output buffers are placed in a High-Z state (2-clock latency)
during a READ cycle. DQM0 corresponds to DQ0–DQ7; DQM1
corresponds to DQ8–DQ15; DQM2 corresponds to DQ16–DQ23;
and DQM3 corresponds to DQ24–DQ31. DQM0–DQM3 are
considered same state when referenced as DQM.
22, 23 J7, H8 BA0, BA1 Input
Bank address input(s): BA0 and BA1 define to which bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
25–27, 60–66,
24
G8, G9, F7, F3,
G1, G2, G3, H1,
H2, J3, G7
A0–A10 Input
Address inputs: A0–A10 are sampled during the ACTIVE
command (row-address A0–A10) and READ/WRITE command
(column-address A0–A7 with A10 defining auto precharge) to
select one location out of the memory array in the respective
bank. A10 is sampled during a PRECHARGE command to
determine whether all banks are to be precharged (A10 HIGH)
or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8, 10,
11, 13, 74, 76,
77, 79, 80, 82,
83, 85, 31, 33,
34, 36, 37, 39,
40, 42, 45, 47,
48, 50, 51, 53,
54, 56
R8, N7, R9, N8,
P9, M8, M7, L8,
L2, M3, M2, P1,
N2, R1, N3, R2,
E8, D7, D8, B9,
C8, A9, C7, A8,
A2, C3, A1, C2,
B1, D2, D3, E2
DQ0–
DQ31
Input/
Ou
tput
Data I/Os: Data bus.
MS-8
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