JBL MS-8 - Functional Block and CPU (DSP Core) Diagram

AUREUS TMS320DA610, TMS320DA601
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS002I − SEPTEMBER 2001 − REVISED OCTOBER 2005
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
functional block and CPU (DSP core) diagram
Test
C67x CPU
Data Path B
B Register File
Instruction Fetch
Instruction Dispatch
Instruction Decode
Data Path A
A Register File
Power-Down
Logic
.L1
†
.S1
†
.M1
†
.D1 .D2 .M2
†
.S2
†
.L2
†
L1P Cache
Direct Mapped
4K Bytes Total
Control
Registers
Control
Logic
L1D Cache
2-Way Set
Associative
4K Bytes Total
In-Circuit
Emulation
Interrupt
Control
DA610 and DA601 Digital Signal Processors
†
In addition to fixed-point instructions, these functional units execute floating-point instructions.
Enhanced
DMA
Controller
(16 channel)
L2 Cache/
Memory
4 Banks
64K Bytes
Total
(4-Way)
Clock Generator,
Oscillator, and PLL
x4 through x25 Multipliers
/1 through /32 Dividers
L2
Memory
DA610:
192K Bytes
DA601:
64K Bytes
R2 ROM
512K
Bytes
Total
EMIF32
McASP1
McASP0
McBSP1
McBSP0
I2C1
I2C0
Timer 1
Timer 0
GP1
GP0
HPI16
Pin Multiplexing
McBSPs interface to:
−SPI Control Port
−High-Speed TDM Codecs
−AC97 Codecs
−Serial EEPROM
EMIF32 interfaces to:
−SDRAM
−SBSRAM
−SRAM,
−ROM/Flash, and
−I/O devices
McASPs interface to:
−I2S Multichannel ADC, DAC, Codec, DIR
−DIT: Multiple Outputs
MS-8
47