JVC UX-P55 - Page 31

(No.22036)1-31
4.8 LC72136N (IC2) : PLL frequency synthesizer
•Pin layout
• Block diagram
• Pin function
1
2
3
4
5
6
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
XT
FM/AM
CE
DI
CLOCK
DO
FM/ST/VCO
AM/FM
SDIN
XT
GND
LPFOUT
LPFIN
PD
VCC
FMIN
AMIN
IFCONT
IFIN
Reference
Driver
Phase
Detector
Charge Pump
Unlock
Detector
Universal
Counter
Swallow Counter
1/16,1/17 4bit
12bit
Programmable
DriverS
Swallow Counter
1/16,1/17 4bit
Data Shift Register & Latch
Power
on
Reset
C
2B
I/F
1/2
782
11
13
21
17
6
5
4
3
15
16
22
1
18
19
20
12
Pin
No.
Symbol I/O Function
1 XT I X'tal oscillator connect (75kHz)
2FM
/AM O LOW:FM mode
3 CE I When data output/input for 4pin(input)
and 6pin(output): H
4 DI I Input for receive the serial data from
controller
5 CLOCK I Sync signal input use
6 DO O Data output for Controller Output port
7 FM/ST/VCO O Low: MW mode
8AM
/FM O Open state after the power on reset
9 LW I/O Input/output port
10 MW I/O Input/output port
11 SDIN I/O Data input/output
12 IFIN I IF counter signal input
13 IFCONT O IF signal output
14 - Not use
15 AMIN I AM Local OSC signal output
16 FMIN I FM Local OSC signal input
17 VCC - Power suplly(VDD=4.5-5.5V)
When power ON:Reset circuit move
18 PD O PLL charge pump output (H: Local
OSC frequency Height than Reference
frequency.L: Low Agreement: Height
impedance)
19 LPFIN I Input for active lowpassfilter of PLL
20 LPFOUT O Output for active lowpassfilter of PLL
21 GND - Connected to GND
22 XT
I X'tal oscillator(75KHz)
Pin
No.
Symbol I/O Function