DR600 Service Manual
Figure 3-7 Processor Internal Circuit
The internal circuit of the processor is as Figure 3-7 shows, which is composed of various serial interfaces
such as 300MHz ARM926EJ MPU、300MHz C674x DSP、DMA controller、SDRAM EMIF interface、EMAC
Ethernet IC RMII interface、McASP digital audio interface and McBSP, SPI, I2C, UART.
U6 is DDR2 SDRAM with the capacity of 1Gb(64Mx16), and it is used to store the running program
codes and various dynamic data.
U7 is NAND FLASH with the capacity of 2GB, and it is used to store the drivers of all the devices,
operation system and application program code which includes the program code of FPGA.
The digital IF signal sent from the FPGA processing receiving unit communicate with the processor U4
via EMA BUS, and it communicate with DAC via the analog SPI interface to process the transmitting and
receiving data, which includes the data framing, filter, interpolation, extracting and etc. to achieve the
calculation and synchronization of frame number. The PLL module inside the FPGA IC will process the
external 12.8MHz, +/-1.5ppm reference clock to generate a 61.44MHz master clock via 24/5 frequency
doubling and frequency division.
The external circuit includes the parts of ADC, DAC, CODEC, AUDIO AMP, ETHERNET, RS232 and etc.
The Analog-Digital Convertor ADC (U22) collects data such as stationary wave signal detection and
power supply voltage detection which are controlled by RF power.
Digital-Analog Convertor DAC (U24) is used for transmitter two point modulation output, and the other
DAC(U27) is used to achieve the band pass adjusting and the RF power amplification control of the RF
receiver, the tuning control of the receiver local oscillation reference clock.
CODEC(U30) achieves the digital-analog converting. It is connected to the OMAP processor via I2S
digital audio interface to achieve the local monitoring, output and input of interposed speech or audio Tx/Rx
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