Pin Symbol Pin Name I/O Pu/Pd STBY Description
73 P21/AN18/SIN0_0/INT06_1/WKUP2 UPDATE_RX I L MCU uart update rx
74 P20/AN19/INT05_0/CROUT_0/MAD24_1 N.C O L Case of OPEN : "I/O"="O", Output LOW
75 VSS VSS VSS
76 VCC VCC VCC
77 P00/TRSTX JTRST I - J-Link emulater
78 P01/TCK/SWCLK JTCK I - J-Link emulater
79 P02/TDI JTDI I - J-Link emulater
80 P03/TMS/SWDIO JTMS O - J-Link emulater
81 P04/TDO/SWO TDO O - J-Link emulater
82
P05/INT00_1/AN20/TRACED0/TIOA5_2/
SIN4_2/MCS5_1
N.C O L Case of OPEN : "I/O"="O", Output LOW
83
P06/INT01_1/AN21/TRACED1/TIOB5_2/
SOT4_2/MCSX4_1
EEPROM_SDA I/O L/H EEPROM Data
84
P07/AN22/ADTG_0/MCLKOUT_1/TRACED2/
SCK4_2
EEPROM_SCL O L/H EEPROM Clock
85
P08/AN23/TRACED3/TIOA0_2/CTS4_2/
MCSX3_1
IPOD_SDA I/O Pu L Apple Chip SDA
86 P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 IPOD_SCL O Pu L Apple Chip SCL
87 P0A/SIN4_0/INT00_2 CD_UBS2 I Pu L CD Data Out ( receive data from CD DSP )
88 P0B/SOT4_0/TIOB6_1 CD_UBS3 O Pu L CD Data In ( send command to CD DSP )
89 P0C/SCK4_0/TIOA6_1 CD_BUCK O Pu L CD Clock
90 P0D/RTS4_0/TIOA3_2/MDQM0_1 CD_CCE O Pu L CD Chip Select
91 P0E/CTS4_0/TIOB3_2//MDQM1_1 CD_DSP_RST O Pu L CD RESET
92
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/
WKUP0
CD_CLOSE_M O L CD Close Motor
93 P63/INT03_0/MWEX_1 CD_OPEN_M O L CD Open Motor
94 P62/SCK5_0/ADTG_3 CD_CLOSE_SW I Pu L CD Close Switch
95 P61/SOT5_0/TIOB2_2/UHCONX CD_OPEN_SW I Pu L CD Open Switch
96
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/
CEC1
CD_LIMIT_SW I Pu L CD Inner Switch
97 VCC VCC VCC
98 P80/UDM0 MT_STBY O Pu L CD Motor Standby
99 P81/UDP0 N.C O L Case of OPEN : "I/O"="O", Output LOW
100 VSS VSS VSS
TC94A92FG (IC100)
Terminal Function
43
DCD-710AE
TC94A92FG (IC17)
㩷
㩷
㪧㫀㫆㪎
㪧㫀㫆㪍
㪧㫀㫆㪌
㪧㫀㫆㪋
㪧㫀㫆㪊
㪧㫀㫆㪉
㪧㫀㫆㪈
㪧㫀㫆㪇
㪭㪪㪪㪄㪉
㪭㪛㪛㪈㪄㪉
㪯㪭㪛㪛㪊
㪯㫆
㪯㫀
㪯㪭㪪㪪㪊
㪛㪭㪪㪪㪊㪣
㪣㫆
㪛㪭㪛㪛㪊㪣
㪛㪭㪛㪛㪊
㪩㫆
㪛㪭㪪㪪㪊㪩
㪍㪇
㪌㪐
㪌㪏
㪌㪎
㪌㪍
㪌㪌
㪌㪋
㪌㪊
㪌㪉
㪌㪈
㪌㪇
㪋㪐
㪋㪏
㪋㪎
㪋㪍
㪋㪌
㪋㪋
㪋㪊
㪋㪉
㪋㪈
㪭㪛㪛㪊
㪍㪈 㪋㪇
㪚㪛㪤㫆㪥㪊
㪙㪬㪪㪇
㪍㪉 㪊㪐
㪧㫀㫆㪈㪋㩷㪆㩷㪚㪛㪤㫆㪥㪉
㪙㪬㪪㪈
㪍㪊 㪊㪏
㪧㫀㫆㪈㪊㩷㪆㩷㪚㪛㪤㫆㪥㪈
㪙㪬㪪㪉
㪍㪋 㪊㪎
㪙㪬㪪㪊
㪍㪌 㪊㪍
㪧㫀㫆㪈㪈
㪙㪬㪚㪢
㪍㪍 㪊㪌
㪧㫀㫆㪈㪇
㪆㪚㪚㪜
㪍㪎 㪊㪋
㪧㫀㫆㪐
㪤㪪
㪍㪏 㪊㪊
㪧㫀㫆㪏
㪆㪩㪪㪫
㪍㪐 㪊㪉
㪭㪛㪛㪈㪄㪊
㪫㪜㪪㪫
㪎㪇 㪊㪈
㪛㪤㫆
㪭㪛㪛㪈㪄㪈
㪎㪈 㪊㪇
㪝㪤㫆㪪
㪭㪪㪪㪄㪈
㪎㪉 㪉㪐
㪝㪤㫆
㪎㪊 㪉㪏
㪭㪪㪪㪄㪊
㪭㪛㪛㪤㪈
㪎㪋 㪉㪎
㪫㪩㫆
㪧㪛㫆
㪎㪌 㪉㪍
㪝㫆㫆
㪫㪤㪘㪯
㪎㪍 㪉㪌
㪘㪭㪛㪛㪊
㪣㪧㪝㪥
㪎㪎 㪉㪋
㪫㪜㫀
㪣㪧㪝㫆
㪎㪏 㪉㪊
㪩㪝㪩㪧
㪧㪭㪩㪜㪝
㪎㪐 㪉㪉
㪩㪝㪱㫀
㪭㪚㫆㪝
㪏㪇 㪉㪈
㪝㪪㪤㫆㪥㫀㪫
㪈
㪉
㪊
㪋
㪌
㪍
㪎
㪏
㪐
㪈㪇
㪈㪈
㪈㪉
㪈㪊
㪈㪋
㪈㪌
㪈㪍
㪈㪎
㪈㪏
㪈㪐
㪉㪇
㪭㪚㫆㫀
㪩㪭㪛㪛㪊
㪪㪣㪚㫆
㪩㪝㫀
㪩㪝㪩㪧㫀
㪩㪝㪜㪨㫆
㪛㪚㫆㪝㪚
㪘㪞㪚㫀
㪩㪝㫆
㪩㪭㪪㪪㪊
㪝㪥㫀㪉
㪝㪥㫀㪈
㪝㪧㫀㪉
㪝㪧㫀㪈
㪫㪧㫀
㪫㪥㫀
㪭㪩㫆
㪘㪭㪪㪪㪊
㪤㪛㫀
㪣㪛㫆
㪫㪚㪐㪋㪘㪐㪉㪝㪞
㩿㪫㫆㫇㩷㪭㫀㪼㫎㪀
44
DCD-710AE
TC94A92FG
Terminal Function
p
Pin
No.
Symbol I/O Description
Default Remarks
1
VCoi
O
3AI/F
DSP VCO - EFM and PLCK Phase difference
signal output pin.
(DSP VCO control voltage inputr pin.)
O
3 state output
2
RVDD3 -
CD-DSP-Power supply for 3.3V RF
amplifier core and PLL circuit
-
3
SLCo
O
3AI/F
EFM slice level output pin㩷
O
Connect capacitor according with se
rvo frequency band.
4
RFi
I
3AI/F
RF signal input pin㩷
I
Selectable Zin 20/10 k:
5
RFRPi
I
3AI/F
㪩㪝㩷㫉㫀㫇㫇㫃㪼㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅 I
6
RFEQo
O
3AI/F
㪩㪝㩷㪼㫈㫌㪸㫃㫀㫑㪼㫉㩷㪺㫀㫉㪺㫌㫀㫋㩷㫆㫌㫋㫇㫌㫋㩷㫇㫀㫅㪅 O
Connect to RFRPi by 0.1uF, to RFi by
4700pF.
7
DCoFC
O
3AI/F
RFEQo offset compensation LPF output O
Connect to Vro by more than 0.015uF
8
AGCi
I
3AI/F
㪩㪝㩷㫊㫀㪾㫅㪸㫃㩷㪘㪞㪚㩷㪸㫄㫇㫃㫀㪽㫀㪼㫉㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅 I
9
RFo
O
3AI/F
㪩㪝㩷㫊㫀㪾㫅㪸㫃㩷㪾㪼㫅㪼㫉㪸㫋㫀㫆㫅㩷㪸㫄㫇㫃㫀㪽㫀㪼㫉㩷㫆㫌㫋㫇㫌㫋㩷㫇㫀㫅 O
10
RVSS3 -
㪞㫉㫆㫌㫅㪻㫀㫅㪾㩷㫇㫀㫅㩷 㪽㫆㫉㩷㪊㪅㪊㩷 㪩㪝㩷 㪸㫄㫇㫃㫀㪽㫀㪼㫉㩷 㪺㫆㫉㪼㩷 and PLL
circuit
-
11
FNI2
I
3AI/F
㪤㪸㫀㫅㩷㪹㪼㪸㫄㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅㩷
㪫㫆㩷㪹㪼㩷㪺㫆㫅㫅㪼㪺㫋㪼㪻㩷㫋㫆㩷㪧㪠㪥㩷㪻㫀㫆㪻㪼㩷㪚㪅
I
12
FNI1
I
3AI/F
㪤㪸㫀㫅㩷㪹㪼㪸㫄㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅㩷
㪫㫆㩷㪹㪼㩷㪺㫆㫅㫅㪼㪺㫋㪼㪻㩷㫋㫆㩷㪧㪠㪥㩷㪻㫀㫆㪻㪼㩷㪘㪅
I
13
FPI2
I
3AI/F
㪤㪸㫀㫅㩷㪹㪼㪸㫄㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅㩷
㪫㫆㩷㪹㪼㩷㪺㫆㫅㫅㪼㪺㫋㪼㪻㩷㫋㫆㩷㪧㪠㪥㩷㪻㫀㫆㪻㪼㩷㪛㪅㩷
I
14
FPI1
I
3AI/F
㪤㪸㫀㫅㩷㪹㪼㪸㫄㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅㩷
㪫㫆㩷㪹㪼㩷㪺㫆㫅㫅㪼㪺㫋㪼㪻㩷㫋㫆㩷㪧㪠㪥㩷㪻㫀㫆㪻㪼㩷㪙㪅
I
15
TPi
I
3AI/F
㪪㫌㪹㩷㪹㪼㪸㫄㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅㩷
㪫㫆㩷㪹㪼㩷㪺㫆㫅㫅㪼㪺㫋㪼㪻㩷㫋㫆㩷㪧㪠㪥㩷㪻㫀㫆㪻㪼㩷㪝㪅
I
16
TNi
I
3AI/F
㪪㫌㪹㩷㪹㪼㪸㫄㩷㫊㫀㪾㫅㪸㫃㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅㩷
㪫㫆㩷㪹㪼㩷㪺㫆㫅㫅㪼㪺㫋㪼㪻㩷㫋㫆㩷㪧㪠㪥㩷㪻㫀㫆㪻㪼㩷㪜㪅
I
17
VRo
O
3AI/F
㪈㪅㪍㪌㩷㪭㩷㫉㪼㪽㪼㫉㪼㫅㪺㪼㩷㫍㫆㫃㫋㪸㪾㪼㩷㫆㫌㫋㫇㫌㫋㩷㫇㫀㫅㪅 O
Connected to PVREF,
And connect to GNG by
0.1uF+100uF.
18
AVSS3 -
Grounding pin for 3.3V CD analog circuits.
-
19
MDi
I
3AI/F
㪤㫆㫅㫀㫋㫆㫉㩷㫇㪿㫆㫋㫆㪻㫀㫆㪻㪼㩷㪸㫄㫇㫃㫀㪽㫀㪼㫉㩷㫀㫅㫇㫌㫋㩷㫇㫀㫅㪅 I
Reference Voltage=178mVtyp.
20
LDo
O
3AI/F
㪣㪸㫊㪼㫉㩷㪻㫀㫆㪻㪼㩷㪸㫄㫇㫃㫀㪽㫀㪼㫉㩷㫆㫌㫋㫇㫌㫋㩷㫇㫀㫅 O
17
Caution in
servicing
Electrical Mechanical Repair Information Updating
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